[llvm] fe49ba8 - [AArch64] Reflow comment in AArch64IselLowering.cpp (NFC).

Florian Hahn via llvm-commits llvm-commits at lists.llvm.org
Fri Sep 30 09:17:29 PDT 2022


Author: Florian Hahn
Date: 2022-09-30T17:17:04+01:00
New Revision: fe49ba84d354a121516e85f76803c7a00876b3d1

URL: https://github.com/llvm/llvm-project/commit/fe49ba84d354a121516e85f76803c7a00876b3d1
DIFF: https://github.com/llvm/llvm-project/commit/fe49ba84d354a121516e85f76803c7a00876b3d1.diff

LOG: [AArch64] Reflow comment in AArch64IselLowering.cpp (NFC).

Added: 
    

Modified: 
    llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index c391974c466b..0d152c68898f 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -18109,7 +18109,9 @@ static SDValue foldTruncStoreOfExt(SelectionDAG &DAG, SDNode *N) {
   return SDValue();
 }
 
-// Perform TBI simplification if supported by the target and try to break up nontemporal loads larger than 256-bits loads for odd types so LDNPQ 256-bit load instructions can be selected.
+// Perform TBI simplification if supported by the target and try to break up
+// nontemporal loads larger than 256-bits loads for odd types so LDNPQ 256-bit
+// load instructions can be selected.
 static SDValue performLOADCombine(SDNode *N,
                                   TargetLowering::DAGCombinerInfo &DCI,
                                   SelectionDAG &DAG,


        


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