[llvm] 1e3c179 - [RISCV] Address post commit review comments from D134881

[Philip Reames via llvm-commits]

Author: Philip Reames
Date: 2022-09-30T08:31:40-07:00
New Revision: 1e3c179519b91953ad127ab558b0b9d64ead3ee4

URL: https://github.com/llvm/llvm-project/commit/1e3c179519b91953ad127ab558b0b9d64ead3ee4
DIFF: https://github.com/llvm/llvm-project/commit/1e3c179519b91953ad127ab558b0b9d64ead3ee4.diff

LOG: [RISCV] Address post commit review comments from D134881

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVISelLowering.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 228270777e3d..67e110252d95 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -9025,7 +9025,7 @@ SDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N,
     // (select (and (x , 0x1) != 0), (z ^ y) ), y -> (-(and (x , 0x1)) & z ) ^ y
     // (select (and (x , 0x1) == 0), y, (z | y) ) -> (-(and (x , 0x1)) & z ) | y
     // (select (and (x , 0x1) != 0), (z | y) ), y -> (-(and (x , 0x1)) & z ) | y
-    if (isNullConstant(RHS) && (CCVal == ISD::SETEQ || CCVal == ISD::SETNE) &&
+    if (isNullConstant(RHS) && ISD::isIntEqualitySetCC(CCVal) &&
         LHS.getOpcode() == ISD::AND && isOneConstant(LHS.getOperand(1))) {
       unsigned Opcode;
       SDValue Src1, Src2;
@@ -9057,7 +9057,7 @@ SDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N,
 
       if (isOrXorPattern()) {
         SDValue Neg;
-        unsigned int CmpSz = LHS.getSimpleValueType().getSizeInBits();
+        unsigned CmpSz = LHS.getSimpleValueType().getSizeInBits();
         // We need mask of all zeros or ones with same size of the other
         // operands.
         if (CmpSz > VT.getSizeInBits())