[PATCH] D134783: [PowerPC] Fix a number of inefficiencies and issues with atomic code gen

[Kai Luo via Phabricator via llvm-commits]

lkail added inline comments.


================
Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.cpp:15754
+    };
+    // Combine branches fed by store conditional instructions (st[bhwd]cx).
+    unsigned StoreWidth = 0;
----------------
Is it missing a test, kinda like
```
define signext i1 @foo(i64* %addr, i64 %newval) {
entry:
  %0 = bitcast i64* %addr to i8*
  br label %while.cond

while.cond:                                       ; preds = %while.body, %entry
  %1 = tail call i32 @llvm.ppc.stdcx(i8* %0, i64 %newval)
  %ok = icmp eq i32 %1, 0
  br i1 %ok, label %end, label %end.0
end:
  ret i1 0
end.0:
  ret i1 1
}
```


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D134783/new/

https://reviews.llvm.org/D134783