[PATCH] D134897: [AMDGPU] Fix V_CMP_CLASS_F16_t16_e64 src1 type.

Thu Sep 29 12:49:00 PDT 2022

dp added a comment.

In D134897#3824823 <https://reviews.llvm.org/D134897#3824823>, @Joe_Nash wrote:

> In D134897#3824780 <https://reviews.llvm.org/D134897#3824780>, @dp wrote:
>
>>> For some reason, we cannot encode inline literals for VSrc_b16.
>>
>> This is true for inline floating-point constants only. Integer inline constants may be used without limitations, so I do not see any problems using VSrc_b16 for src1.
>
> Before D133723 <https://reviews.llvm.org/D133723>, inline floating-point constants were allowed. Arguably they should be allowed ( https://developer.amd.com/wp-content/resources/RDNA2_Shader_ISA_November2020.pdf "Note that the S1 has a format of f16 since floating point literal
> constants are interpreted as 16 bit value for this opcode"), though I don't know if they would be emitted by codegen.

Thanks, I see. I forgot that there are special opcodes with 16 bit integer operands which should be handled differently. I'll take a closer look at the issue.

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https://reviews.llvm.org/D134897