[PATCH] D134897: [AMDGPU] Fix V_CMP_CLASS_F16_t16_e64 src1 type.

[Joe Nash via Phabricator via llvm-commits]

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For V_CMP_CLASS_F16_t16_e64 and V_CMPX_CLASS_F16_t16_e64,
https://reviews.llvm.org/D133723 changed the value type of src1 from i32 to i16.
These src1 operands are 16 bits, therefore need to be encoded as true16
operands. So the _e32 type was correctly set to VGPR_32_Lo128.
In _e64 form the operand class went from
VSrc_b32 to VSrc_b16. For some reason, we cannot encode inline literals for
VSrc_b16, see 5f5f566b265db00f577ead268400d99f34ba9cdd <https://reviews.llvm.org/rG5f5f566b265db00f577ead268400d99f34ba9cdd>. In this phase of
the true16 implementation, VSrc_b16 and VSrc_b32 are still similar,
except from that quirk of inlines. So set the operand class to regain
that function.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D134897

Files:
  llvm/lib/Target/AMDGPU/VOPCInstructions.td
  llvm/test/MC/AMDGPU/gfx11_asm_vop3c.s
  llvm/test/MC/AMDGPU/gfx11_asm_vop3cx.s
  llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3c.txt
  llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3cx.txt


Index: llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3cx.txt
===================================================================
--- llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3cx.txt
+++ llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3cx.txt
@@ -4,6 +4,9 @@
 # GFX11: v_cmpx_class_f16_e64 v1, v2             ; encoding: [0x7e,0x00,0xfd,0xd4,0x01,0x05,0x02,0x00]
 0x7e,0x00,0xfd,0xd4,0x01,0x05,0x02,0x00
 
+# GFX11: v_cmpx_class_f16_e64 v1, 0.5            ; encoding: [0x7e,0x00,0xfd,0xd4,0x01,0xe1,0x01,0x00]
+0x7e,0x00,0xfd,0xd4,0x01,0xe1,0x01,0x00
+
 # GFX11: v_cmpx_class_f16_e64 v255, v2           ; encoding: [0x7e,0x00,0xfd,0xd4,0xff,0x05,0x02,0x00]
 0x7e,0x00,0xfd,0xd4,0xff,0x05,0x02,0x00
 
Index: llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3c.txt
===================================================================
--- llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3c.txt
+++ llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3c.txt
@@ -5,6 +5,10 @@
 # W64: v_cmp_class_f16_e64 s[10:11], v1, v2      ; encoding: [0x0a,0x00,0x7d,0xd4,0x01,0x05,0x02,0x00]
 0x0a,0x00,0x7d,0xd4,0x01,0x05,0x02,0x00
 
+# W32: v_cmp_class_f16_e64 s10, v1, 0.5           ; encoding: [0x0a,0x00,0x7d,0xd4,0x01,0xe1,0x01,0x00]
+# W64: v_cmp_class_f16_e64 s[10:11], v1, 0.5     ; encoding: [0x0a,0x00,0x7d,0xd4,0x01,0xe1,0x01,0x00]
+0x0a,0x00,0x7d,0xd4,0x01,0xe1,0x01,0x00
+
 # W32: v_cmp_class_f16_e64 s10, v255, v2         ; encoding: [0x0a,0x00,0x7d,0xd4,0xff,0x05,0x02,0x00]
 # W64: v_cmp_class_f16_e64 s[10:11], v255, v2    ; encoding: [0x0a,0x00,0x7d,0xd4,0xff,0x05,0x02,0x00]
 0x0a,0x00,0x7d,0xd4,0xff,0x05,0x02,0x00
Index: llvm/test/MC/AMDGPU/gfx11_asm_vop3cx.s
===================================================================
--- llvm/test/MC/AMDGPU/gfx11_asm_vop3cx.s
+++ llvm/test/MC/AMDGPU/gfx11_asm_vop3cx.s
@@ -46,6 +46,9 @@
 v_cmpx_class_f16_e64 -|0xfe0b|, vcc_hi
 // GFX11: encoding: [0x7e,0x01,0xfd,0xd4,0xff,0xd6,0x00,0x20,0x0b,0xfe,0x00,0x00]
 
+v_cmpx_class_f16_e64 v1, 0.5
+// GFX11: encoding: [0x7e,0x00,0xfd,0xd4,0x01,0xe1,0x01,0x00]
+
 v_cmpx_class_f32_e64 v1, v2
 // GFX11: encoding: [0x7e,0x00,0xfe,0xd4,0x01,0x05,0x02,0x00]
 
Index: llvm/test/MC/AMDGPU/gfx11_asm_vop3c.s
===================================================================
--- llvm/test/MC/AMDGPU/gfx11_asm_vop3c.s
+++ llvm/test/MC/AMDGPU/gfx11_asm_vop3c.s
@@ -59,6 +59,10 @@
 // W32: encoding: [0x7b,0x00,0x7d,0xd4,0xfd,0xd4,0x00,0x00]
 // W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
 
+v_cmp_class_f16_e64 s[10:11], v1, 0.5
+// W64: encoding: [0x0a,0x00,0x7d,0xd4,0x01,0xe1,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
 v_cmp_class_f16_e64 s[10:11], v1, v2
 // W64: encoding: [0x0a,0x00,0x7d,0xd4,0x01,0x05,0x02,0x00]
 // W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
Index: llvm/lib/Target/AMDGPU/VOPCInstructions.td
===================================================================
--- llvm/lib/Target/AMDGPU/VOPCInstructions.td
+++ llvm/lib/Target/AMDGPU/VOPCInstructions.td
@@ -792,6 +792,7 @@
   def _t16 : VOPC_Class_Profile<sched, f16, i16> {
     let IsTrue16 = 1;
     let Src1RC32 = RegisterOperand<getVregSrcForVT_t16<Src1VT>.ret>;
+    let Src1RC64 = VSrc_b32;
     let Src0DPP = getVregSrcForVT_t16<Src0VT>.ret;
     let Src1DPP = getVregSrcForVT_t16<Src1VT>.ret;
     let Src2DPP = getVregSrcForVT_t16<Src2VT>.ret;
@@ -819,6 +820,7 @@
   def _t16 : VOPC_Class_NoSdst_Profile<sched, f16, i16> {
     let IsTrue16 = 1;
     let Src1RC32 = RegisterOperand<getVregSrcForVT_t16<Src1VT>.ret>;
+    let Src1RC64 = VSrc_b32;
     let Src0DPP = getVregSrcForVT_t16<Src0VT>.ret;
     let Src1DPP = getVregSrcForVT_t16<Src1VT>.ret;
     let Src2DPP = getVregSrcForVT_t16<Src2VT>.ret;


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