[PATCH] D134890: [X86] Pre-commit test case showing bug in combineOr (X86ISelLowering.cpp)

[Bjorn Pettersson via Phabricator via llvm-commits]

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In combineOr (X86ISelLowering.cpp) there is a DAG combine that rewrite
a "(0 - SetCC) | C" pattern into something simpler given that a LEA
can be used. Another requirement is that C has some specific value,
for example 1 or 7. When doing that check it is using a 32-bit
unsigned variable to store the value of C. So for a 64-bit OR this
could miscompile in case any of the 32 most significant bits in C
are set.

This patch adds a test case to show this miscompile bug.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D134890

Files:
  llvm/test/CodeGen/X86/or-lea.ll


Index: llvm/test/CodeGen/X86/or-lea.ll
===================================================================
--- llvm/test/CodeGen/X86/or-lea.ll
+++ llvm/test/CodeGen/X86/or-lea.ll
@@ -792,3 +792,34 @@
   %or = or i64 %sext, 8
   ret i64 %or
 }
+
+define i64 @or_large_constant(i64 %x) {
+; X86-LABEL: or_large_constant:
+; X86:       # %bb.0: # %entry
+; X86-NEXT:    xorl %edx, %edx
+; X86-NEXT:    movl $1, %eax
+; X86-NEXT:    cmpl {{[0-9]+}}(%esp), %eax
+; X86-NEXT:    movl $0, %eax
+; X86-NEXT:    sbbl {{[0-9]+}}(%esp), %eax
+; X86-NEXT:    setl %al
+; X86-NEXT:    movzbl %al, %eax
+; X86-NEXT:    negl %eax
+; X86-NEXT:    sbbl %edx, %edx
+; X86-NEXT:    orl $1, %eax
+; X86-NEXT:    orl $128, %edx
+; X86-NEXT:    retl
+;
+; X64-LABEL: or_large_constant:
+; X64:       # %bb.0: # %entry
+; X64-NEXT:    xorl %eax, %eax
+; X64-NEXT:    cmpq $2, %rdi
+; X64-NEXT:    setl %al
+; X64-NEXT:    leaq -1(%rax,%rax), %rax
+; X64-NEXT:    retq
+entry:
+  %cmp = icmp sgt i64 %x, 1
+  %zext = zext i1 %cmp to i64
+  %sub = sub i64 0, %zext
+  %or = or i64 %sub, 549755813889   ; 0x8000000001
+  ret i64 %or
+}


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