[PATCH] D134884: [RISCV] Add a LocalStackSlotAllocation test

luxufan via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Thu Sep 29 08:25:41 PDT 2022


StephenFan created this revision.
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Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D134884

Files:
  llvm/test/CodeGen/RISCV/local-stack-slot-allocation.ll


Index: llvm/test/CodeGen/RISCV/local-stack-slot-allocation.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/RISCV/local-stack-slot-allocation.ll
@@ -0,0 +1,33 @@
+
+; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s | FileCheck %s
+
+; This test case test the LocalStackSlotAllocation pass that use a base register 
+; for the frame index that its offset is out-of-range (for RISC-V. the immediate
+; is 12 bits for the load store instruction (excludes vector load / store))
+; TODO: Enable LocalStackSlotAllocation pass.
+define void @use_frame_base_reg() {
+; CHECK-LABEL: use_frame_base_reg
+; CHECK:       # %bb.0
+; CHECK-NEXT:     lui a0, 24
+; CHECK-NEXT:     addiw a0, a0, 1712
+; CHECK-NEXT:     sub sp, sp, a0
+; CHECK-NEXT:     .cfi_def_cfa_offset 100016
+; CHECK-NEXT:     lui a0, 24
+; CHECK-NEXT:     addiw a0, a0, 1708
+; CHECK-NEXT:     add a0, sp, a0
+; CHECK-NEXT:     lb a0, 0(a0)
+; CHECK-NEXT:     lui a0, 24
+; CHECK-NEXT:     addiw a0, a0, 1704
+; CHECK-NEXT:     add a0, sp, a0
+; CHECK-NEXT:     lb a0, 0(a0)
+; CHECK-NEXT:     lui a0, 24
+; CHECK-NEXT:     addiw a0, a0, 1712
+; CHECK-NEXT:     add sp, sp, a0
+; CHECK-NEXT:     ret
+  %va = alloca i8, align 4
+  %va1 = alloca i8, align 4
+  %large = alloca [ 100000 x i8 ]
+  %argp.cur = load volatile i8, i8* %va, align 4
+  %argp.next = load volatile i8, i8* %va1, align 4
+  ret void
+}


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