[PATCH] D134876: [ValueTracking] Fix CannotBeOrderedLessThanZero() for fdiv (PR58046)

[Nikita Popov via Phabricator via llvm-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGaa25c92f33e4: [ValueTracking] Fix CannotBeOrderedLessThanZero() for fdiv (PR58046) (authored by nikic).

Changed prior to commit:
  https://reviews.llvm.org/D134876?vs=463879&id=463909#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D134876/new/

https://reviews.llvm.org/D134876

Files:
  llvm/lib/Analysis/ValueTracking.cpp
  llvm/test/Transforms/InstSimplify/floating-point-compare.ll


Index: llvm/test/Transforms/InstSimplify/floating-point-compare.ll
===================================================================
--- llvm/test/Transforms/InstSimplify/floating-point-compare.ll
+++ llvm/test/Transforms/InstSimplify/floating-point-compare.ll
@@ -999,10 +999,14 @@
   ret <2 x i1> %cmp
 }
 
-; FIXME: Miscompile.
+; TODO: This could fold to true.
 define i1 @pr58046(i64 %arg) {
 ; CHECK-LABEL: @pr58046(
-; CHECK-NEXT:    ret i1 false
+; CHECK-NEXT:    [[FP:%.*]] = uitofp i64 [[ARG:%.*]] to double
+; CHECK-NEXT:    [[MUL:%.*]] = fmul double -0.000000e+00, [[FP]]
+; CHECK-NEXT:    [[DIV:%.*]] = fdiv double 1.000000e+00, [[MUL]]
+; CHECK-NEXT:    [[CMP:%.*]] = fcmp oeq double [[DIV]], 0xFFF0000000000000
+; CHECK-NEXT:    ret i1 [[CMP]]
 ;
   %fp = uitofp i64 %arg to double
   %mul = fmul double -0.000000e+00, %fp
Index: llvm/lib/Analysis/ValueTracking.cpp
===================================================================
--- llvm/lib/Analysis/ValueTracking.cpp
+++ llvm/lib/Analysis/ValueTracking.cpp
@@ -3629,14 +3629,23 @@
   // Unsigned integers are always nonnegative.
   case Instruction::UIToFP:
     return true;
-  case Instruction::FMul:
   case Instruction::FDiv:
-    // X * X is always non-negative or a NaN.
     // X / X is always exactly 1.0 or a NaN.
     if (I->getOperand(0) == I->getOperand(1) &&
         (!SignBitOnly || cast<FPMathOperator>(I)->hasNoNaNs()))
       return true;
 
+    // Set SignBitOnly for RHS, because X / -0.0 is -Inf (or NaN).
+    return cannotBeOrderedLessThanZeroImpl(I->getOperand(0), TLI, SignBitOnly,
+                                           Depth + 1) &&
+           cannotBeOrderedLessThanZeroImpl(I->getOperand(1), TLI,
+                                           /*SignBitOnly*/ true, Depth + 1);
+  case Instruction::FMul:
+    // X * X is always non-negative or a NaN.
+    if (I->getOperand(0) == I->getOperand(1) &&
+        (!SignBitOnly || cast<FPMathOperator>(I)->hasNoNaNs()))
+      return true;
+
     [[fallthrough]];
   case Instruction::FAdd:
   case Instruction::FRem:


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