[PATCH] D132559: [AArch64] Add support for 128-bit non temporal loads.

[Florian Hahn via Phabricator via llvm-commits]

fhahn added a comment.

Thanks for getting rid of the excessive codegen regressions from the earlier version!  IIUC now we should get at most an extra `mov` instruction to combine the 2 loaded values into a single vector. IMO this is a reasonable trade-off between user request & codegen.

@dmgreen WDYT? If there still are concerns about the extra `mov` instruction, we could make this opt-in with a target feature.



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Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:5467
 
-  if (LoadNode->getMemoryVT() != MVT::v4i8)
+  if ((VT != MVT::v4i16 && VT != MVT::v4i32) || LoadNode->getMemoryVT() != MVT::v4i8)
     return SDValue();
----------------
nit: this needs formatting.


Repository:
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  https://reviews.llvm.org/D132559/new/

https://reviews.llvm.org/D132559