[PATCH] D134526: [AMDGPU] Preserve only the inactive lanes of scratch vgprs

[Matt Arsenault via Phabricator via llvm-commits]

arsenm accepted this revision.
arsenm added inline comments.
This revision is now accepted and ready to land.


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Comment at: llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp:285-288
+void SIMachineFunctionInfo::splitWWMSpillRegisters(
+    MachineFunction &MF,
+    SmallVectorImpl<std::pair<Register, int>> &CalleeSavedRegs,
+    SmallVectorImpl<std::pair<Register, int>> &ScratchRegs) const {
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I don't really like having to split these into two arrays like this but I don't have a better suggestion


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Comment at: llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp:291
+  for (auto &Reg : WWMSpills) {
+    if (TRI->isCalleeSavedPhysReg(Reg.first, MF))
+      CalleeSavedRegs.push_back(Reg);
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arsenm wrote:
> This needs to check the MRI callee saved regs, not TRI directly for dynamically changed CSRs
Actually I've seen this mistake too many times. We should probably rename the TRI version and hide it


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D134526/new/

https://reviews.llvm.org/D134526