[PATCH] D134635: [AMDGPU][GlobalISel] Add Shift/Shufflevector Combine

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


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Comment at: llvm/lib/Target/AMDGPU/AMDGPURegBankCombiner.cpp:336-337
+    MachineInstr &MI, Register &Reg) {
+  // Fold (G_TRUNC (G_LSHR (G_BITCAST (G_SHUFFLE_VECTOR %a, %b, shufflemask(1,
+  // ?))), K)) into a simple (G_TRUNC (G_BITCAST(%a)) if the shift amount (K) is
+  // 1/2 of the destination type and the vector types have 2 elements.
----------------
Should break up this comment to avoid wrapping the pattern bit


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Comment at: llvm/lib/Target/AMDGPU/AMDGPURegBankCombiner.cpp:366
+  if (MRI.getType(LHS).getSizeInBits() != TruncSrcSize ||
+      MRI.getType(RHS).getSizeInBits() != TruncSrcSize)
+    return false;
----------------
LHS and RHS have to have the same type


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Comment at: llvm/lib/Target/AMDGPU/AMDGPURegBankCombiner.cpp:392
+  B.buildBitcast(NewSrc, Reg);
+  MI.getOperand(1).setReg(NewSrc);
+}
----------------
Need to call the observer if modifying the argument list


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Comment at: llvm/test/CodeGen/AMDGPU/GlobalISel/combine-trunc-shift-shufflevector.mir:272
+    $vgpr0_vgpr1 = COPY %7
+...
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Could use a test where the shuffle has multiple users


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D134635/new/

https://reviews.llvm.org/D134635