[llvm] d743aff - [InstCombine] add tests for shuffle-of-shuffle; NFC

[Sanjay Patel via llvm-commits]

Author: Sanjay Patel
Date: 2022-09-28T11:56:27-04:00
New Revision: d743aff7906784c054a0a7e9bc5db0011b8fe947

URL: https://github.com/llvm/llvm-project/commit/d743aff7906784c054a0a7e9bc5db0011b8fe947
DIFF: https://github.com/llvm/llvm-project/commit/d743aff7906784c054a0a7e9bc5db0011b8fe947.diff

LOG: [InstCombine] add tests for shuffle-of-shuffle; NFC

Added: 
    

Modified: 
    llvm/test/Transforms/InstCombine/shuffle_select.ll

Removed: 
    


################################################################################
diff  --git a/llvm/test/Transforms/InstCombine/shuffle_select.ll b/llvm/test/Transforms/InstCombine/shuffle_select.ll
index 03886b9f0eb8..9133a1fbabd6 100644
--- a/llvm/test/Transforms/InstCombine/shuffle_select.ll
+++ b/llvm/test/Transforms/InstCombine/shuffle_select.ll
@@ -1528,3 +1528,92 @@ define <4 x i32> @PR41419(<4 x i32> %v) {
   ret <4 x i32> %s
 }
 
+define <5 x i4> @sel_common_op_commute0(<5 x i4> %x, <5 x i4> %y) {
+; CHECK-LABEL: @sel_common_op_commute0(
+; CHECK-NEXT:    [[S1:%.*]] = shufflevector <5 x i4> [[X:%.*]], <5 x i4> [[Y:%.*]], <5 x i32> <i32 undef, i32 6, i32 2, i32 undef, i32 undef>
+; CHECK-NEXT:    [[S2:%.*]] = shufflevector <5 x i4> [[X]], <5 x i4> [[S1]], <5 x i32> <i32 0, i32 6, i32 7, i32 3, i32 4>
+; CHECK-NEXT:    ret <5 x i4> [[S2]]
+;
+  %s1 = shufflevector <5 x i4> %x, <5 x i4> %y, <5 x i32> <i32 0, i32 6, i32 2, i32 3, i32 9>
+  %s2 = shufflevector <5 x i4> %x, <5 x i4> %s1, <5 x i32> <i32 0, i32 6, i32 7, i32 3, i32 4>
+  ret <5 x i4> %s2
+}
+
+define <5 x i4> @sel_common_op_commute1(<5 x i4> %x, <5 x i4> %y) {
+; CHECK-LABEL: @sel_common_op_commute1(
+; CHECK-NEXT:    [[S1:%.*]] = shufflevector <5 x i4> [[Y:%.*]], <5 x i4> [[X:%.*]], <5 x i32> <i32 undef, i32 6, i32 2, i32 undef, i32 undef>
+; CHECK-NEXT:    [[S2:%.*]] = shufflevector <5 x i4> [[X]], <5 x i4> [[S1]], <5 x i32> <i32 0, i32 6, i32 7, i32 3, i32 4>
+; CHECK-NEXT:    ret <5 x i4> [[S2]]
+;
+  %s1 = shufflevector <5 x i4> %y, <5 x i4> %x, <5 x i32> <i32 0, i32 6, i32 2, i32 3, i32 9>
+  %s2 = shufflevector <5 x i4> %x, <5 x i4> %s1, <5 x i32> <i32 0, i32 6, i32 7, i32 3, i32 4>
+  ret <5 x i4> %s2
+}
+
+define <5 x i4> @sel_common_op_commute2(<5 x i4> %x, <5 x i4> %y) {
+; CHECK-LABEL: @sel_common_op_commute2(
+; CHECK-NEXT:    [[S1:%.*]] = shufflevector <5 x i4> [[X:%.*]], <5 x i4> [[Y:%.*]], <5 x i32> <i32 0, i32 undef, i32 undef, i32 3, i32 9>
+; CHECK-NEXT:    [[S2:%.*]] = shufflevector <5 x i4> [[S1]], <5 x i4> [[X]], <5 x i32> <i32 0, i32 6, i32 7, i32 3, i32 4>
+; CHECK-NEXT:    ret <5 x i4> [[S2]]
+;
+  %s1 = shufflevector <5 x i4> %x, <5 x i4> %y, <5 x i32> <i32 0, i32 6, i32 2, i32 3, i32 9>
+  %s2 = shufflevector <5 x i4> %s1, <5 x i4> %x, <5 x i32> <i32 0, i32 6, i32 7, i32 3, i32 4>
+  ret <5 x i4> %s2
+}
+
+define <5 x i4> @sel_common_op_commute3(<5 x i4> %x, <5 x i4> %y) {
+; CHECK-LABEL: @sel_common_op_commute3(
+; CHECK-NEXT:    [[S1:%.*]] = shufflevector <5 x i4> [[Y:%.*]], <5 x i4> [[X:%.*]], <5 x i32> <i32 0, i32 undef, i32 undef, i32 3, i32 9>
+; CHECK-NEXT:    [[S2:%.*]] = shufflevector <5 x i4> [[S1]], <5 x i4> [[X]], <5 x i32> <i32 0, i32 6, i32 7, i32 3, i32 4>
+; CHECK-NEXT:    ret <5 x i4> [[S2]]
+;
+  %s1 = shufflevector <5 x i4> %y, <5 x i4> %x, <5 x i32> <i32 0, i32 6, i32 2, i32 3, i32 9>
+  %s2 = shufflevector <5 x i4> %s1, <5 x i4> %x, <5 x i32> <i32 0, i32 6, i32 7, i32 3, i32 4>
+  ret <5 x i4> %s2
+}
+
+define <5 x i4> @sel_common_op_commute3_poison_mask_elts(<5 x i4> %x, <5 x i4> %y) {
+; CHECK-LABEL: @sel_common_op_commute3_poison_mask_elts(
+; CHECK-NEXT:    [[S1:%.*]] = shufflevector <5 x i4> [[Y:%.*]], <5 x i4> [[X:%.*]], <5 x i32> <i32 0, i32 undef, i32 undef, i32 undef, i32 9>
+; CHECK-NEXT:    [[S2:%.*]] = shufflevector <5 x i4> [[S1]], <5 x i4> [[X]], <5 x i32> <i32 0, i32 6, i32 undef, i32 undef, i32 4>
+; CHECK-NEXT:    ret <5 x i4> [[S2]]
+;
+  %s1 = shufflevector <5 x i4> %y, <5 x i4> %x, <5 x i32> <i32 0, i32 6, i32 2, i32 poison, i32 9>
+  %s2 = shufflevector <5 x i4> %s1, <5 x i4> %x, <5 x i32> <i32 0, i32 6, i32 poison, i32 3, i32 4>
+  ret <5 x i4> %s2
+}
+
+define <5 x i4> @sel_not_common_op_commute3(<5 x i4> %x, <5 x i4> %y, <5 x i4> %z) {
+; CHECK-LABEL: @sel_not_common_op_commute3(
+; CHECK-NEXT:    [[S1:%.*]] = shufflevector <5 x i4> [[Y:%.*]], <5 x i4> [[Z:%.*]], <5 x i32> <i32 0, i32 undef, i32 undef, i32 3, i32 9>
+; CHECK-NEXT:    [[S2:%.*]] = shufflevector <5 x i4> [[S1]], <5 x i4> [[X:%.*]], <5 x i32> <i32 0, i32 6, i32 7, i32 3, i32 4>
+; CHECK-NEXT:    ret <5 x i4> [[S2]]
+;
+  %s1 = shufflevector <5 x i4> %y, <5 x i4> %z, <5 x i32> <i32 0, i32 6, i32 2, i32 3, i32 9>
+  %s2 = shufflevector <5 x i4> %s1, <5 x i4> %x, <5 x i32> <i32 0, i32 6, i32 7, i32 3, i32 4>
+  ret <5 x i4> %s2
+}
+
+define <5 x i4> @not_sel_common_op(<5 x i4> %x, <5 x i4> %y) {
+; CHECK-LABEL: @not_sel_common_op(
+; CHECK-NEXT:    [[S1:%.*]] = shufflevector <5 x i4> [[Y:%.*]], <5 x i4> [[X:%.*]], <5 x i32> <i32 undef, i32 6, i32 undef, i32 3, i32 9>
+; CHECK-NEXT:    [[S2:%.*]] = shufflevector <5 x i4> [[S1]], <5 x i4> [[X]], <5 x i32> <i32 1, i32 6, i32 7, i32 3, i32 4>
+; CHECK-NEXT:    ret <5 x i4> [[S2]]
+;
+  %s1 = shufflevector <5 x i4> %y, <5 x i4> %x, <5 x i32> <i32 0, i32 6, i32 2, i32 3, i32 9>
+  %s2 = shufflevector <5 x i4> %s1, <5 x i4> %x, <5 x i32> <i32 1, i32 6, i32 7, i32 3, i32 4>
+  ret <5 x i4> %s2
+}
+
+define <4 x i32> @sel_common_op_extra_use(<4 x i32> %x, <4 x i32> %y) {
+; CHECK-LABEL: @sel_common_op_extra_use(
+; CHECK-NEXT:    [[S1:%.*]] = shufflevector <4 x i32> [[Y:%.*]], <4 x i32> [[X:%.*]], <4 x i32> <i32 0, i32 5, i32 2, i32 7>
+; CHECK-NEXT:    call void @use_v4i32(<4 x i32> [[S1]])
+; CHECK-NEXT:    [[S2:%.*]] = shufflevector <4 x i32> [[S1]], <4 x i32> [[X]], <4 x i32> <i32 0, i32 1, i32 6, i32 7>
+; CHECK-NEXT:    ret <4 x i32> [[S2]]
+;
+  %s1 = shufflevector <4 x i32> %y, <4 x i32> %x, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
+  call void @use_v4i32(<4 x i32> %s1)
+  %s2 = shufflevector <4 x i32> %s1, <4 x i32> %x, <4 x i32> <i32 0, i32 1, i32 6, i32 7>
+  ret <4 x i32> %s2
+}