[PATCH] D133421: [AArch64] break non-temporal loads over 256 into 256-loads and a smaller load

[Florian Hahn via Phabricator via llvm-commits]

fhahn added a comment.

Thanks for the update. 2 more small comments, but I'll fix them before committing the change on your behalf.



================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:18082
 
+// Break up nontermporal loads larger than 256-bits loads so LDNPQ 256-bit load
+// instruction can be selected.
----------------
Looks like there's another typo: `nontermporal -> nontemporal`


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:18125
+    LoadOpsChain.push_back(SDValue(cast<SDNode>(NewLoad), 1));
+  
+  }
----------------
The newline was meant to go after the `}` to separate it from the next block, not before it.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D133421/new/

https://reviews.llvm.org/D133421