[PATCH] D134723: [AMDGPU] Set memory bound occupancy based on addressable VGPRs

[Jay Foad via Phabricator via llvm-commits]

foad added a comment.

> i.e. it should be higher than 4 in many cases to avoid spilling.

As I understand it: the scheduler came up with a schedule that had a max register pressure of 128. For some reason the register allocator (or other post-scheduler passes) failed to meet this limit and actually tried to use more than 128 registers. Normally this would mean that we miss the scheduler's occupancy target, but because 128 was the maximum number of usable registers (on GFX11 before D133723 <https://reviews.llvm.org/D133723>) we spilled instead.

Perhaps it is worth trying to understand *why* we failed to meet the scheduler's estimated limit of 128 registers? It may not be possible for the scheduler to accurately estimate the final register usage in all cases, but perhaps there are some simple problems that we could fix to make the estimate more reliable?


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https://reviews.llvm.org/D134723