[PATCH] D133850: [AArch64] Improve codegen for "trunc <4 x i64> to <4 x i8>" for all cases

[Sheng via Phabricator via llvm-commits]

0x59616e added inline comments.


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:17589-17591
+    assert((SimpleVT == MVT::v4i16 || SimpleVT == MVT::v2i32 ||
+            SimpleVT == MVT::v8i8) &&
+           "Expect SimpleVT to be one of v4i16 or v2i32 or v8i8");
----------------
0x59616e wrote:
> mingmingl wrote:
> > (I wrote `assert` in the previous work as well)
> > 
> > On a second thought, it's more future proof to bail out if type is not one of {v4i116, v2i32, v8i8} in this context, given that UZP1 SDNode definition doesn't require vector element type to be integer (i.e. v4f16 is ok for compilation)
> > 
> > Something like
> > 
> > ```
> > Type val;
> > switch (SimpleVT) {
> >   case valid-case1:
> >     val = ...;
> >     break;
> >   case valid-case2;
> >     val = ...
> >     break;
> >   default:
> >     break;
> > }
> > 
> > if val is not set
> >   bail out
> > ```
> > 
> > 
> I use switch to implement this logic at line 17892 in the latest diff.
Correct: 17896.


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  https://reviews.llvm.org/D133850/new/

https://reviews.llvm.org/D133850