[llvm] 50f6c4f - [RISCV] Expand strided store test coverage for missing opts during codegen

[Philip Reames via llvm-commits]

Author: Philip Reames
Date: 2022-09-27T11:20:36-07:00
New Revision: 50f6c4fcdf99c34fb062b7c234bc5dfa3d8a2c14

URL: https://github.com/llvm/llvm-project/commit/50f6c4fcdf99c34fb062b7c234bc5dfa3d8a2c14
DIFF: https://github.com/llvm/llvm-project/commit/50f6c4fcdf99c34fb062b7c234bc5dfa3d8a2c14.diff

LOG: [RISCV] Expand strided store test coverage for missing opts during codegen

Added: 
    

Modified: 
    llvm/test/CodeGen/RISCV/rvv/mscatter-combine.ll

Removed: 
    


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diff  --git a/llvm/test/CodeGen/RISCV/rvv/mscatter-combine.ll b/llvm/test/CodeGen/RISCV/rvv/mscatter-combine.ll
index 7991eb98571c..86e7f2e06b02 100644
--- a/llvm/test/CodeGen/RISCV/rvv/mscatter-combine.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/mscatter-combine.ll
@@ -33,4 +33,107 @@ define void @complex_gep(ptr %p, <vscale x 2 x i64> %vec.ind, <vscale x 2 x i1>
   ret void
 }
 
+define void @strided_store_zero_start(i64 %n, ptr %p) {
+; RV32-LABEL: strided_store_zero_start:
+; RV32:       # %bb.0:
+; RV32-NEXT:    vsetvli a0, zero, e64, m1, ta, mu
+; RV32-NEXT:    vid.v v8
+; RV32-NEXT:    vsetvli zero, zero, e32, mf2, ta, mu
+; RV32-NEXT:    vnsrl.wi v8, v8, 0
+; RV32-NEXT:    li a0, 48
+; RV32-NEXT:    vmul.vx v8, v8, a0
+; RV32-NEXT:    addi a0, a2, 32
+; RV32-NEXT:    vsetvli zero, zero, e64, m1, ta, mu
+; RV32-NEXT:    vmv.v.i v9, 0
+; RV32-NEXT:    vsoxei32.v v9, (a0), v8
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: strided_store_zero_start:
+; RV64:       # %bb.0:
+; RV64-NEXT:    vsetvli a0, zero, e64, m1, ta, mu
+; RV64-NEXT:    vid.v v8
+; RV64-NEXT:    li a0, 56
+; RV64-NEXT:    vmul.vx v8, v8, a0
+; RV64-NEXT:    addi a0, a1, 36
+; RV64-NEXT:    vmv.v.i v9, 0
+; RV64-NEXT:    vsoxei64.v v9, (a0), v8
+; RV64-NEXT:    ret
+  %step = tail call <vscale x 1 x i64> @llvm.experimental.stepvector.nxv1i64()
+  %gep = getelementptr inbounds %struct, ptr %p, <vscale x 1 x i64> %step, i32 6
+  tail call void @llvm.masked.scatter.nxv1i64.nxv1p0(<vscale x 1 x i64> zeroinitializer, <vscale x 1 x ptr> %gep, i32 8, <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i32 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer))
+  ret void
+}
+
+define void @strided_store_offset_start(i64 %n, ptr %p) {
+; RV32-LABEL: strided_store_offset_start:
+; RV32:       # %bb.0:
+; RV32-NEXT:    addi sp, sp, -16
+; RV32-NEXT:    .cfi_def_cfa_offset 16
+; RV32-NEXT:    vsetvli a3, zero, e64, m1, ta, mu
+; RV32-NEXT:    sw a1, 12(sp)
+; RV32-NEXT:    sw a0, 8(sp)
+; RV32-NEXT:    addi a0, sp, 8
+; RV32-NEXT:    vlse64.v v8, (a0), zero
+; RV32-NEXT:    vid.v v9
+; RV32-NEXT:    vadd.vv v8, v9, v8
+; RV32-NEXT:    vsetvli zero, zero, e32, mf2, ta, mu
+; RV32-NEXT:    vnsrl.wi v8, v8, 0
+; RV32-NEXT:    li a0, 48
+; RV32-NEXT:    vmul.vx v8, v8, a0
+; RV32-NEXT:    addi a0, a2, 32
+; RV32-NEXT:    vsetvli zero, zero, e64, m1, ta, mu
+; RV32-NEXT:    vmv.v.i v9, 0
+; RV32-NEXT:    vsoxei32.v v9, (a0), v8
+; RV32-NEXT:    addi sp, sp, 16
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: strided_store_offset_start:
+; RV64:       # %bb.0:
+; RV64-NEXT:    vsetvli a2, zero, e64, m1, ta, mu
+; RV64-NEXT:    vid.v v8
+; RV64-NEXT:    vadd.vx v8, v8, a0
+; RV64-NEXT:    li a0, 56
+; RV64-NEXT:    vmul.vx v8, v8, a0
+; RV64-NEXT:    addi a0, a1, 36
+; RV64-NEXT:    vmv.v.i v9, 0
+; RV64-NEXT:    vsoxei64.v v9, (a0), v8
+; RV64-NEXT:    ret
+  %step = tail call <vscale x 1 x i64> @llvm.experimental.stepvector.nxv1i64()
+  %.splatinsert = insertelement <vscale x 1 x i64> poison, i64 %n, i64 0
+  %.splat = shufflevector <vscale x 1 x i64> %.splatinsert, <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer
+  %add = add <vscale x 1 x i64> %step, %.splat
+  %gep = getelementptr inbounds %struct, ptr %p, <vscale x 1 x i64> %add, i32 6
+  tail call void @llvm.masked.scatter.nxv1i64.nxv1p0(<vscale x 1 x i64> zeroinitializer, <vscale x 1 x ptr> %gep, i32 8, <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i32 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer))
+  ret void
+}
+
+define void @stride_one_store(i64 %n, ptr %p) {
+; RV32-LABEL: stride_one_store:
+; RV32:       # %bb.0:
+; RV32-NEXT:    vsetvli a0, zero, e64, m1, ta, mu
+; RV32-NEXT:    vid.v v8
+; RV32-NEXT:    vsetvli zero, zero, e32, mf2, ta, mu
+; RV32-NEXT:    vnsrl.wi v8, v8, 0
+; RV32-NEXT:    vsll.vi v8, v8, 3
+; RV32-NEXT:    vsetvli zero, zero, e64, m1, ta, mu
+; RV32-NEXT:    vmv.v.i v9, 0
+; RV32-NEXT:    vsoxei32.v v9, (a2), v8
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: stride_one_store:
+; RV64:       # %bb.0:
+; RV64-NEXT:    vsetvli a0, zero, e64, m1, ta, mu
+; RV64-NEXT:    vid.v v8
+; RV64-NEXT:    vsll.vi v8, v8, 3
+; RV64-NEXT:    vmv.v.i v9, 0
+; RV64-NEXT:    vsoxei64.v v9, (a1), v8
+; RV64-NEXT:    ret
+  %step = tail call <vscale x 1 x i64> @llvm.experimental.stepvector.nxv1i64()
+  %gep = getelementptr inbounds i64, ptr %p, <vscale x 1 x i64> %step
+  tail call void @llvm.masked.scatter.nxv1i64.nxv1p0(<vscale x 1 x i64> zeroinitializer, <vscale x 1 x ptr> %gep, i32 8, <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i32 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer))
+  ret void
+}
+
+declare <vscale x 1 x i64> @llvm.experimental.stepvector.nxv1i64()
 declare void @llvm.masked.scatter.nxv2i32.nxv2p0(<vscale x 2 x i32>, <vscale x 2 x ptr>, i32, <vscale x 2 x i1>)
+declare void @llvm.masked.scatter.nxv1i64.nxv1p0(<vscale x 1 x i64>, <vscale x 1 x ptr>, i32, <vscale x 1 x i1>)