[PATCH] D134701: [RISCV][ISel] Remove the commutative flag on SUB

[Quentin Colombet via Phabricator via llvm-commits]

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I wasn't able to produce a testcase for that because right now VWSUB is only generated from VWSUB_W and to trigger the commutative bug we would need to turn that VWSUB_W into VWSUB while having the splat value on the LHS, which is currently not matched by the existing combine.

Presumably we could hit this issue directly with vwsub intrinsics, but I didn't know how to produce a splat value for a vscale type and I don't know if it is possible to use the intrinsic without the vscale type.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D134701

Files:
  llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td


Index: llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
===================================================================
--- llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
+++ llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
@@ -253,8 +253,8 @@
 def riscv_vwmulsu_vl : SDNode<"RISCVISD::VWMULSU_VL", SDT_RISCVVWBinOp_VL>;
 def riscv_vwadd_vl :  SDNode<"RISCVISD::VWADD_VL",  SDT_RISCVVWBinOp_VL, [SDNPCommutative]>;
 def riscv_vwaddu_vl : SDNode<"RISCVISD::VWADDU_VL", SDT_RISCVVWBinOp_VL, [SDNPCommutative]>;
-def riscv_vwsub_vl :  SDNode<"RISCVISD::VWSUB_VL",  SDT_RISCVVWBinOp_VL, [SDNPCommutative]>;
-def riscv_vwsubu_vl : SDNode<"RISCVISD::VWSUBU_VL", SDT_RISCVVWBinOp_VL, [SDNPCommutative]>;
+def riscv_vwsub_vl :  SDNode<"RISCVISD::VWSUB_VL",  SDT_RISCVVWBinOp_VL, []>;
+def riscv_vwsubu_vl : SDNode<"RISCVISD::VWSUBU_VL", SDT_RISCVVWBinOp_VL, []>;
 
 def SDT_RISCVVNBinOp_VL : SDTypeProfile<1, 5, [SDTCisVec<0>,
                                                SDTCisSameNumEltsAs<0, 1>,


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