[PATCH] D134684: [LegalizeTypes][AMDGPU][Mips][RISCV][X86] Mask shift amounts in ExpandShiftWithUnknownAmountBit.

[Craig Topper via Phabricator via llvm-commits]

craig.topper updated this revision to Diff 463055.
craig.topper added a comment.

Fix shift amount. This reduces the number of tests changed.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D134684/new/

https://reviews.llvm.org/D134684

Files:
  llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
  llvm/test/CodeGen/Mips/llvm-ir/ashr.ll
  llvm/test/CodeGen/Mips/llvm-ir/lshr.ll
  llvm/test/CodeGen/Mips/llvm-ir/shl.ll
  llvm/test/CodeGen/RISCV/shifts.ll
  llvm/test/CodeGen/SystemZ/shift-12.ll

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