[PATCH] D134684: [LegalizeTypes][AMDGPU][Mips][RISCV][X86] Mask shift amounts in ExpandShiftWithUnknownAmountBit.

[Amanieu d'Antras via Phabricator via llvm-commits]

Amanieu added inline comments.


================
Comment at: llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp:2802
+  AmtLack = DAG.getNode(ISD::AND, dl, ShTy, AmtLack, NVTBitsM1);
+  Amt = DAG.getNode(ISD::AND, dl, ShTy, AmtLack, NVTBitsM1);
+
----------------
Should this be Amt instead of AmtLack in the argument?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D134684/new/

https://reviews.llvm.org/D134684