[PATCH] D134639: [VP][RISCV] Add vp.maxnum and vp.minnum intrinsics and RISC-V support.

[Yeting Kuo via Phabricator via llvm-commits]

fakepaper56 marked 4 inline comments as done.
fakepaper56 added inline comments.


================
Comment at: llvm/docs/LangRef.rst:18901
+
+      %t = minnum <4 x float> %a, %b
+      %also.r = select <4 x i1> %mask, <4 x float> %t, <4 x float> poison
----------------
craig.topper wrote:
> There is no minnum instruction so this should be `%t = call <4 x float> @llvm.minnum.v4f32(<4 x float> %a, <4 x float> %b))`
Done.


================
Comment at: llvm/docs/LangRef.rst:18950
+
+      %t = maxnum <4 x float> %a, %b
+      %also.r = select <4 x i1> %mask, <4 x float> %t, <4 x float> poison
----------------
craig.topper wrote:
> same comment as minnum
Done.


================
Comment at: llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp:1074
   case ISD::FMUL: case ISD::VP_FMUL:
-  case ISD::FMINNUM:
-  case ISD::FMAXNUM:
+  case ISD::FMINNUM: case ISD::VP_FMINNUM:
+  case ISD::FMAXNUM: case ISD::VP_FMAXNUM:
----------------
craig.topper wrote:
> Are there tests for this?
I added vfmin_vv_v32f64 and vfmax_vv_v32f64 to test that.


================
Comment at: llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp:3927
   case ISD::SRL: case ISD::VP_LSHR:
-  case ISD::FMINNUM:
-  case ISD::FMAXNUM:
+  case ISD::FMINNUM: case ISD::VP_FMINNUM:
+  case ISD::FMAXNUM: case ISD::VP_FMAXNUM:
----------------
craig.topper wrote:
> Are there tests for this?
Thank your reminder. I added `vfmin_vv_v15f64` and `vfmax_vv_v15f64` to test that.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D134639/new/

https://reviews.llvm.org/D134639