[llvm] 0ce96e0 - [AMDGPU] Move SIModeRegisterDefaults to SI MFI
Stanislav Mekhanoshin via llvm-commits
llvm-commits at lists.llvm.org
Mon Sep 26 13:20:39 PDT 2022
Author: Stanislav Mekhanoshin
Date: 2022-09-26T13:20:24-07:00
New Revision: 0ce96e06ee0226938e723bd0c8e16e3d2d51f203
URL: https://github.com/llvm/llvm-project/commit/0ce96e06ee0226938e723bd0c8e16e3d2d51f203
DIFF: https://github.com/llvm/llvm-project/commit/0ce96e06ee0226938e723bd0c8e16e3d2d51f203.diff
LOG: [AMDGPU] Move SIModeRegisterDefaults to SI MFI
It does not belong to a general AMDGPU MFI.
Differential Revision: https://reviews.llvm.org/D134666
Added:
Modified:
llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
llvm/lib/Target/AMDGPU/AMDGPUMachineFunction.cpp
llvm/lib/Target/AMDGPU/AMDGPUMachineFunction.h
llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
Removed:
################################################################################
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
index 4818514191d5..8e45ea73af29 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
@@ -1630,12 +1630,12 @@ SDValue AMDGPUTargetLowering::LowerDIVREM24(SDValue Op, SelectionDAG &DAG,
SDValue fqneg = DAG.getNode(ISD::FNEG, DL, FltVT, fq);
MachineFunction &MF = DAG.getMachineFunction();
- const AMDGPUMachineFunction *MFI = MF.getInfo<AMDGPUMachineFunction>();
+ const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
// float fr = mad(fqneg, fb, fa);
unsigned OpCode = !Subtarget->hasMadMacF32Insts() ?
(unsigned)ISD::FMA :
- !MFI->getMode().allFP32Denormals() ?
+ (!MFI || !MFI->getMode().allFP32Denormals()) ?
(unsigned)ISD::FMAD :
(unsigned)AMDGPUISD::FMAD_FTZ;
SDValue fr = DAG.getNode(OpCode, DL, FltVT, fqneg, fb, fa);
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUMachineFunction.cpp b/llvm/lib/Target/AMDGPU/AMDGPUMachineFunction.cpp
index f5e12fd960d0..2b9755c4a3ec 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUMachineFunction.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUMachineFunction.cpp
@@ -17,7 +17,7 @@
using namespace llvm;
AMDGPUMachineFunction::AMDGPUMachineFunction(const MachineFunction &MF)
- : Mode(MF.getFunction()), IsEntryFunction(AMDGPU::isEntryFunctionCC(
+ : IsEntryFunction(AMDGPU::isEntryFunctionCC(
MF.getFunction().getCallingConv())),
IsModuleEntryFunction(
AMDGPU::isModuleEntryFunctionCC(MF.getFunction().getCallingConv())),
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUMachineFunction.h b/llvm/lib/Target/AMDGPU/AMDGPUMachineFunction.h
index 97db8b7eb8d6..e8e2d693d4b0 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUMachineFunction.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPUMachineFunction.h
@@ -45,9 +45,6 @@ class AMDGPUMachineFunction : public MachineFunctionInfo {
/// stages.
Align DynLDSAlign;
- // State of MODE register, assumed FP mode.
- AMDGPU::SIModeRegisterDefaults Mode;
-
// Kernels + shaders. i.e. functions called by the hardware and not called
// by other functions.
bool IsEntryFunction = false;
@@ -80,10 +77,6 @@ class AMDGPUMachineFunction : public MachineFunctionInfo {
return GDSSize;
}
- AMDGPU::SIModeRegisterDefaults getMode() const {
- return Mode;
- }
-
bool isEntryFunction() const {
return IsEntryFunction;
}
diff --git a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
index 9176e85568ee..99967507a200 100644
--- a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
@@ -31,6 +31,7 @@ using namespace llvm;
SIMachineFunctionInfo::SIMachineFunctionInfo(const MachineFunction &MF)
: AMDGPUMachineFunction(MF),
+ Mode(MF.getFunction()),
BufferPSV(static_cast<const AMDGPUTargetMachine &>(MF.getTarget())),
ImagePSV(static_cast<const AMDGPUTargetMachine &>(MF.getTarget())),
GWSResourcePSV(static_cast<const AMDGPUTargetMachine &>(MF.getTarget())),
diff --git a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
index 5105587617fd..aff679deb069 100644
--- a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
+++ b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
@@ -351,6 +351,9 @@ template <> struct MappingTraits<SIMachineFunctionInfo> {
class SIMachineFunctionInfo final : public AMDGPUMachineFunction {
friend class GCNTargetMachine;
+ // State of MODE register, assumed FP mode.
+ AMDGPU::SIModeRegisterDefaults Mode;
+
// Registers that may be reserved for spilling purposes. These may be the same
// as the input registers.
Register ScratchRSrcReg = AMDGPU::PRIVATE_RSRC_REG;
@@ -552,6 +555,10 @@ class SIMachineFunctionInfo final : public AMDGPUMachineFunction {
WWMReservedRegs.insert(Reg);
}
+ AMDGPU::SIModeRegisterDefaults getMode() const {
+ return Mode;
+ }
+
ArrayRef<SIRegisterInfo::SpilledReg>
getSGPRToVGPRSpills(int FrameIndex) const {
auto I = SGPRToVGPRSpills.find(FrameIndex);
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