[PATCH] D133116: [AArch64][SVE] Optimise repeated floating-point complex patterns to splat

[Matt Devereau via Phabricator via llvm-commits]

MattDevereau planned changes to this revision.
MattDevereau marked 2 inline comments as done.
MattDevereau added a comment.

@paulwalker-arm I've moved the new function to DAG combine, and have somewhat side-graded the current complex pattern matching logic to work with the nodes present after DAG combine, which are different from the nodes previously in ISel lowering. I'll focus on implementing your other suggestion of enabling scalable vectors for `AArch64ISD::DUPLANE##` nodes, feel free to ignore this review for the time being



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Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:10786-10787
+// Simplify patterns like
+// INSERT_SUBVECTOR(BUILD_VECTOR(f32 a, f32 b, f32 a, f32 b))
+// to SPLAT_VECTOR(f64(a, b))
+SDValue useWideSplatForBuildVectorRepeatedComplexPattern(SDValue Op,
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paulwalker-arm wrote:
> As mentioned below I don't believe this transform is save outside of the context of how it's used in the `AArch64ISD::DUPLANE128` case you care about. Hence my do it as a DAG combine suggestion.
I've moved this to be a DAG combine inside `performDupLane128Combine`


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Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:10802-10808
+  unsigned NumOperands = BuildVector.getNumOperands();
+  if (NumOperands < 4 || NumOperands % 2 != 0)
+    return SDValue();
+  for (unsigned i = 0; i < NumOperands / 2; i++) {
+    if (BuildVector.getOperand(i) != BuildVector.getOperand(i + 2))
+      return SDValue();
+  }
----------------
paulwalker-arm wrote:
> `ISD::BUILD_VECTOR` has its own class `BuildVectorSDNode` that provides `getRepeatedSequence()`, which can probably help here and perhaps mean we can cover more cases?
This worked perfectly when I tried it, although moving the new function inside DAGCombine meant that the `ISD::BUILD_VECTOR` node has already been lowered to an `ISD::INSERT_SUBVECTOR` node.
I've changed the code to something similar here but with ISD::INSERT_SUBVECTOR, if you also have a suggestion similar to the buildvector improvement then that would be optimal. Regardless, this might not be a big deal as I'm focusing on your other suggestion of exposing scalable vector types for  `AArch64ISD::DUPLANE##` for now


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https://reviews.llvm.org/D133116