[PATCH] D134646: [AArch64] Add a target feature for AArch64StorePairSuppress

[Dave Green via Phabricator via llvm-commits]

dmgreen created this revision.
dmgreen added reviewers: t.p.northover, fhahn, labrinea, Allen, samtebbs.
Herald added subscribers: hiraditya, kristof.beyls.
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dmgreen requested review of this revision.
Herald added a project: LLVM.

The AArch64StorePairSuppress pass prevents the creation of STP under some heuristics. Unfortunately it often prevents the creation of STP in cases where it is obviously beneficial, and it doesn't match my understanding of scheduling/cpu pipelining to prevent the creation of STP. From some benchmarking, even on an in-order cpu where the scheduling is most important I don't see it giving better results. In general the lower instruction count for STP would be expected to give a slightly better cycle count.

As the pass specifically mentions the cyclone cpu, this patch adds a target feature for FeatureStorePairSuppress, enabled for all the Apple cpus. This has the effect of disabling it for all other cpus. (Alternative options are to disable it for all cpus, or disable it for less).


https://reviews.llvm.org/D134646

Files:
  llvm/lib/Target/AArch64/AArch64.td
  llvm/lib/Target/AArch64/AArch64StorePairSuppress.cpp
  llvm/test/CodeGen/AArch64/aarch64-a57-fp-load-balancing.ll
  llvm/test/CodeGen/AArch64/argument-blocks-array-of-struct.ll
  llvm/test/CodeGen/AArch64/arm64-windows-calls.ll
  llvm/test/CodeGen/AArch64/ldrpre-ldr-merge.mir
  llvm/test/CodeGen/AArch64/storepairsuppress_minsize.ll

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