[PATCH] D134635: [AMDGPU][GlobalISel] Add Shift/Shufflevector Combine

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added a comment.

Another thing worth thinking about is whether we should really be using legal vector_shuffle at all. The DAG path doesn't use it. Given that we have such a restricted set of shuffles (only 0, 1), it may still make sense to keep lowering to simple BUILD_VECTORs with 2 elements



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Comment at: llvm/lib/Target/AMDGPU/AMDGPURegBankCombiner.cpp:355-362
+  MachineInstr *ShiftOp = getDefIgnoringCopies(MI.getOperand(1).getReg(), MRI);
+  if (ShiftOp->getOpcode() != AMDGPU::G_BITCAST)
+    return false;
+
+  // The bitcast src is a SHUFFLE_VECTOR.
+  ShiftOp = getDefIgnoringCopies(ShiftOp->getOperand(1).getReg(), MRI);
+  if (ShiftOp->getOpcode() != AMDGPU::G_SHUFFLE_VECTOR)
----------------
Should use mi_match


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Comment at: llvm/lib/Target/AMDGPU/AMDGPURegBankCombiner.cpp:382
+  B.buildBitcast(MI.getOperand(0).getReg(), Reg);
+  MI.removeFromParent();
+}
----------------
eraseFromParent


Repository:
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  https://reviews.llvm.org/D134635/new/

https://reviews.llvm.org/D134635