[llvm] ad6fe32 - [LoongArch] Support 'generic' as a valid CPU name

[Weining Lu via llvm-commits]

Author: WANG Xuerui
Date: 2022-09-26T10:20:13+08:00
New Revision: ad6fe32032a6229e0c40510e9bed419a01c695b3

URL: https://github.com/llvm/llvm-project/commit/ad6fe32032a6229e0c40510e9bed419a01c695b3
DIFF: https://github.com/llvm/llvm-project/commit/ad6fe32032a6229e0c40510e9bed419a01c695b3.diff

LOG: [LoongArch] Support 'generic' as a valid CPU name

As the LoongArch port is largely modeled after RISCV it has the same
behavior of not accepting `generic` as a CPU name. For better
compatibility with consumers of LLVM (e.g. mesa) follow D121149's suit
and treat `generic` the same as an empty CPU name.

Differential Revision: https://reviews.llvm.org/D134412

Added: 
    llvm/test/CodeGen/LoongArch/cpu-name-generic.ll

Modified: 
    llvm/lib/Target/LoongArch/LoongArch.td
    llvm/lib/Target/LoongArch/LoongArchSubtarget.cpp
    llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchMCTargetDesc.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/LoongArch/LoongArch.td b/llvm/lib/Target/LoongArch/LoongArch.td
index bf465c27ef99..07b347b05636 100644
--- a/llvm/lib/Target/LoongArch/LoongArch.td
+++ b/llvm/lib/Target/LoongArch/LoongArch.td
@@ -100,6 +100,10 @@ include "LoongArchInstrInfo.td"
 def : ProcessorModel<"generic-la32", NoSchedModel, []>;
 def : ProcessorModel<"generic-la64", NoSchedModel, [Feature64Bit]>;
 
+// Support generic for compatibility with other targets. The triple will be used
+// to change to the appropriate la32/la64 version.
+def : ProcessorModel<"generic", NoSchedModel, []>;
+
 def : ProcessorModel<"la464", NoSchedModel, [Feature64Bit,
                                              FeatureExtLASX,
                                              FeatureExtLVZ,

diff  --git a/llvm/lib/Target/LoongArch/LoongArchSubtarget.cpp b/llvm/lib/Target/LoongArch/LoongArchSubtarget.cpp
index ff84e7c8cc1f..6edf59c9f7d1 100644
--- a/llvm/lib/Target/LoongArch/LoongArchSubtarget.cpp
+++ b/llvm/lib/Target/LoongArch/LoongArchSubtarget.cpp
@@ -27,7 +27,7 @@ LoongArchSubtarget &LoongArchSubtarget::initializeSubtargetDependencies(
     const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS,
     StringRef ABIName) {
   bool Is64Bit = TT.isArch64Bit();
-  if (CPU.empty())
+  if (CPU.empty() || CPU == "generic")
     CPU = Is64Bit ? "generic-la64" : "generic-la32";
 
   if (TuneCPU.empty())

diff  --git a/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchMCTargetDesc.cpp b/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchMCTargetDesc.cpp
index ea52e7d5cc6b..942e667bc261 100644
--- a/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchMCTargetDesc.cpp
+++ b/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchMCTargetDesc.cpp
@@ -54,7 +54,7 @@ static MCInstrInfo *createLoongArchMCInstrInfo() {
 
 static MCSubtargetInfo *
 createLoongArchMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) {
-  if (CPU.empty())
+  if (CPU.empty() || CPU == "generic")
     CPU = TT.isArch64Bit() ? "la464" : "generic-la32";
   return createLoongArchMCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, FS);
 }

diff  --git a/llvm/test/CodeGen/LoongArch/cpu-name-generic.ll b/llvm/test/CodeGen/LoongArch/cpu-name-generic.ll
new file mode 100644
index 000000000000..1129d9fcb254
--- /dev/null
+++ b/llvm/test/CodeGen/LoongArch/cpu-name-generic.ll
@@ -0,0 +1,29 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mcpu=generic < %s \
+; RUN:   | FileCheck %s --check-prefix=LA32
+; RUN: llc --mtriple=loongarch32 --mcpu=generic-la32 < %s \
+; RUN:   | FileCheck %s --check-prefix=LA32
+; RUN: llc --mtriple=loongarch64 --mcpu=generic < %s \
+; RUN:   | FileCheck %s --check-prefix=LA64
+; RUN: llc --mtriple=loongarch64 --mcpu=generic-la64 < %s \
+; RUN:   | FileCheck %s --check-prefix=LA64
+
+;; The CPU name "generic" should map to the corresponding concrete names
+;; according to the target triple's bitness.
+define i64 @f(i64 signext %a, i64 signext %b) {
+; LA32-LABEL: f:
+; LA32:       # %bb.0:
+; LA32-NEXT:    add.w $a1, $a1, $a3
+; LA32-NEXT:    add.w $a2, $a0, $a2
+; LA32-NEXT:    sltu $a0, $a2, $a0
+; LA32-NEXT:    add.w $a1, $a1, $a0
+; LA32-NEXT:    move $a0, $a2
+; LA32-NEXT:    ret
+;
+; LA64-LABEL: f:
+; LA64:       # %bb.0:
+; LA64-NEXT:    add.d $a0, $a0, $a1
+; LA64-NEXT:    ret
+  %1 = add nsw i64 %a, %b
+  ret i64 %1
+}