[PATCH] D131260: [DAG] select Cond, -1, C --> or (sext Cond), C if Cond is MVT::i1

Amaury SECHET via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Sat Sep 24 17:45:31 PDT 2022

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deadalnix added a comment.

@RKSimon I'll try what you suggest tomorrow. I've been sick so things are moving slowly on my end. Apologies.


Repository:
  rG LLVM Github Monorepo

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https://reviews.llvm.org/D131260

Previous message: [PATCH] D131260: [DAG] select Cond, -1, C --> or (sext Cond), C if Cond is MVT::i1
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