[llvm] 2b187ef - [ARM] Fix check lines in memcpy-inline.ll test. NFC
David Green via llvm-commits
llvm-commits at lists.llvm.org
Sat Sep 24 13:29:56 PDT 2022
Author: David Green
Date: 2022-09-24T21:29:41+01:00
New Revision: 2b187effbd65ec795689f93e78c42fc9ea34b706
URL: https://github.com/llvm/llvm-project/commit/2b187effbd65ec795689f93e78c42fc9ea34b706
DIFF: https://github.com/llvm/llvm-project/commit/2b187effbd65ec795689f93e78c42fc9ea34b706.diff
LOG: [ARM] Fix check lines in memcpy-inline.ll test. NFC
Commit c442698 updated the check lines in this file, but did so in a
way that removed a number of the existing checks, as the
update_llc_test_checks script does not understand all triples. This
fixes it up as needed to keep testing Thumb1 code.
Added:
Modified:
llvm/test/CodeGen/ARM/memcpy-inline.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/ARM/memcpy-inline.ll b/llvm/test/CodeGen/ARM/memcpy-inline.ll
index 8761e43866167..f4ed4fe0b7bfb 100644
--- a/llvm/test/CodeGen/ARM/memcpy-inline.ll
+++ b/llvm/test/CodeGen/ARM/memcpy-inline.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=thumbv7-apple-ios -mcpu=cortex-a8 -pre-RA-sched=source -disable-post-ra | FileCheck %s
-; RUN: llc < %s -mtriple=thumbv6m-apple-ios -mcpu=cortex-m0 -pre-RA-sched=source -disable-post-ra -mattr=+strict-align | FileCheck %s -check-prefix=CHECK-T1
+; RUN: llc < %s -mtriple=thumbv6m-none-eabi -mcpu=cortex-m0 -pre-RA-sched=source -disable-post-ra -mattr=+strict-align | FileCheck %s --check-prefix=CHECK-T1
%struct.x = type { i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8 }
@src = external global %struct.x
@@ -33,6 +33,27 @@ define i32 @t0() {
; CHECK-NEXT: vstr d16, [r0]
; CHECK-NEXT: movs r0, #0
; CHECK-NEXT: bx lr
+;
+; CHECK-T1-LABEL: t0:
+; CHECK-T1: @ %bb.0: @ %entry
+; CHECK-T1-NEXT: ldr r0, .LCPI0_0
+; CHECK-T1-NEXT: ldrb r1, [r0, #10]
+; CHECK-T1-NEXT: ldr r2, .LCPI0_1
+; CHECK-T1-NEXT: strb r1, [r2, #10]
+; CHECK-T1-NEXT: ldrh r1, [r0, #8]
+; CHECK-T1-NEXT: strh r1, [r2, #8]
+; CHECK-T1-NEXT: ldr r1, [r0]
+; CHECK-T1-NEXT: ldr r0, [r0, #4]
+; CHECK-T1-NEXT: str r1, [r2]
+; CHECK-T1-NEXT: str r0, [r2, #4]
+; CHECK-T1-NEXT: movs r0, #0
+; CHECK-T1-NEXT: bx lr
+; CHECK-T1-NEXT: .p2align 2
+; CHECK-T1-NEXT: @ %bb.1:
+; CHECK-T1-NEXT: .LCPI0_0:
+; CHECK-T1-NEXT: .long src
+; CHECK-T1-NEXT: .LCPI0_1:
+; CHECK-T1-NEXT: .long dst
entry:
call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 8 getelementptr inbounds (%struct.x, %struct.x* @dst, i32 0, i32 0), i8* align 8 getelementptr inbounds (%struct.x, %struct.x* @src, i32 0, i32 0), i32 11, i1 false)
ret i32 0
@@ -51,6 +72,19 @@ define void @t1(i8* nocapture %C) nounwind {
; CHECK-NEXT: vld1.8 {d16, d17}, [r1]
; CHECK-NEXT: vst1.8 {d16, d17}, [r0]
; CHECK-NEXT: bx lr
+;
+; CHECK-T1-LABEL: t1:
+; CHECK-T1: @ %bb.0: @ %entry
+; CHECK-T1-NEXT: .save {r7, lr}
+; CHECK-T1-NEXT: push {r7, lr}
+; CHECK-T1-NEXT: ldr r1, .LCPI1_0
+; CHECK-T1-NEXT: movs r2, #31
+; CHECK-T1-NEXT: bl __aeabi_memcpy
+; CHECK-T1-NEXT: pop {r7, pc}
+; CHECK-T1-NEXT: .p2align 2
+; CHECK-T1-NEXT: @ %bb.1:
+; CHECK-T1-NEXT: .LCPI1_0:
+; CHECK-T1-NEXT: .long .L.str1
entry:
tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %C, i8* getelementptr inbounds ([31 x i8], [31 x i8]* @.str1, i64 0, i64 0), i64 31, i1 false)
ret void
@@ -71,6 +105,19 @@ define void @t2(i8* nocapture %C) nounwind {
; CHECK-NEXT: movt r1, #72
; CHECK-NEXT: str r1, [r0]
; CHECK-NEXT: bx lr
+;
+; CHECK-T1-LABEL: t2:
+; CHECK-T1: @ %bb.0: @ %entry
+; CHECK-T1-NEXT: .save {r7, lr}
+; CHECK-T1-NEXT: push {r7, lr}
+; CHECK-T1-NEXT: ldr r1, .LCPI2_0
+; CHECK-T1-NEXT: movs r2, #36
+; CHECK-T1-NEXT: bl __aeabi_memcpy
+; CHECK-T1-NEXT: pop {r7, pc}
+; CHECK-T1-NEXT: .p2align 2
+; CHECK-T1-NEXT: @ %bb.1:
+; CHECK-T1-NEXT: .LCPI2_0:
+; CHECK-T1-NEXT: .long .L.str2
entry:
tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %C, i8* getelementptr inbounds ([36 x i8], [36 x i8]* @.str2, i64 0, i64 0), i64 36, i1 false)
ret void
@@ -88,6 +135,19 @@ define void @t3(i8* nocapture %C) nounwind {
; CHECK-NEXT: vldr d16, [r1]
; CHECK-NEXT: vst1.8 {d16}, [r0]
; CHECK-NEXT: bx lr
+;
+; CHECK-T1-LABEL: t3:
+; CHECK-T1: @ %bb.0: @ %entry
+; CHECK-T1-NEXT: .save {r7, lr}
+; CHECK-T1-NEXT: push {r7, lr}
+; CHECK-T1-NEXT: ldr r1, .LCPI3_0
+; CHECK-T1-NEXT: movs r2, #24
+; CHECK-T1-NEXT: bl __aeabi_memcpy
+; CHECK-T1-NEXT: pop {r7, pc}
+; CHECK-T1-NEXT: .p2align 2
+; CHECK-T1-NEXT: @ %bb.1:
+; CHECK-T1-NEXT: .LCPI3_0:
+; CHECK-T1-NEXT: .long .L.str3
entry:
tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %C, i8* getelementptr inbounds ([24 x i8], [24 x i8]* @.str3, i64 0, i64 0), i64 24, i1 false)
ret void
@@ -105,6 +165,19 @@ define void @t4(i8* nocapture %C) nounwind {
; CHECK-NEXT: movs r1, #32
; CHECK-NEXT: strh r1, [r0]
; CHECK-NEXT: bx lr
+;
+; CHECK-T1-LABEL: t4:
+; CHECK-T1: @ %bb.0: @ %entry
+; CHECK-T1-NEXT: .save {r7, lr}
+; CHECK-T1-NEXT: push {r7, lr}
+; CHECK-T1-NEXT: ldr r1, .LCPI4_0
+; CHECK-T1-NEXT: movs r2, #18
+; CHECK-T1-NEXT: bl __aeabi_memcpy
+; CHECK-T1-NEXT: pop {r7, pc}
+; CHECK-T1-NEXT: .p2align 2
+; CHECK-T1-NEXT: @ %bb.1:
+; CHECK-T1-NEXT: .LCPI4_0:
+; CHECK-T1-NEXT: .long .L.str4
entry:
tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %C, i8* getelementptr inbounds ([18 x i8], [18 x i8]* @.str4, i64 0, i64 0), i64 18, i1 false)
ret void
@@ -120,6 +193,19 @@ define void @t5(i8* nocapture %C) nounwind {
; CHECK-NEXT: movt r1, #22866
; CHECK-NEXT: str r1, [r0]
; CHECK-NEXT: bx lr
+;
+; CHECK-T1-LABEL: t5:
+; CHECK-T1: @ %bb.0: @ %entry
+; CHECK-T1-NEXT: .save {r7, lr}
+; CHECK-T1-NEXT: push {r7, lr}
+; CHECK-T1-NEXT: ldr r1, .LCPI5_0
+; CHECK-T1-NEXT: movs r2, #7
+; CHECK-T1-NEXT: bl __aeabi_memcpy
+; CHECK-T1-NEXT: pop {r7, pc}
+; CHECK-T1-NEXT: .p2align 2
+; CHECK-T1-NEXT: @ %bb.1:
+; CHECK-T1-NEXT: .LCPI5_0:
+; CHECK-T1-NEXT: .long .L.str5
entry:
tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %C, i8* getelementptr inbounds ([7 x i8], [7 x i8]* @.str5, i64 0, i64 0), i64 7, i1 false)
ret void
@@ -143,6 +229,29 @@ define void @t6() nounwind {
; CHECK-NEXT: vld1.16 {d16}, [r0]
; CHECK-NEXT: vst1.16 {d16}, [r1]
; CHECK-NEXT: bx lr
+;
+; CHECK-T1-LABEL: t6:
+; CHECK-T1: @ %bb.0: @ %entry
+; CHECK-T1-NEXT: ldr r0, .LCPI6_0
+; CHECK-T1-NEXT: movs r1, #88
+; CHECK-T1-NEXT: strh r1, [r0, #12]
+; CHECK-T1-NEXT: ldr r1, .LCPI6_1
+; CHECK-T1-NEXT: ldr r2, .LCPI6_2
+; CHECK-T1-NEXT: ldr r3, .LCPI6_3
+; CHECK-T1-NEXT: str r3, [r0]
+; CHECK-T1-NEXT: str r2, [r0, #4]
+; CHECK-T1-NEXT: str r1, [r0, #8]
+; CHECK-T1-NEXT: bx lr
+; CHECK-T1-NEXT: .p2align 2
+; CHECK-T1-NEXT: @ %bb.1:
+; CHECK-T1-NEXT: .LCPI6_0:
+; CHECK-T1-NEXT: .long spool.splbuf
+; CHECK-T1-NEXT: .LCPI6_1:
+; CHECK-T1-NEXT: .long 1482184792 @ 0x58585858
+; CHECK-T1-NEXT: .LCPI6_2:
+; CHECK-T1-NEXT: .long 1483567663 @ 0x586d722f
+; CHECK-T1-NEXT: .LCPI6_3:
+; CHECK-T1-NEXT: .long 1886221359 @ 0x706d742f
entry:
call void @llvm.memcpy.p0i8.p0i8.i64(i8* getelementptr inbounds ([512 x i8], [512 x i8]* @spool.splbuf, i64 0, i64 0), i8* getelementptr inbounds ([14 x i8], [14 x i8]* @.str6, i64 0, i64 0), i64 14, i1 false)
ret void
@@ -156,6 +265,18 @@ define void @t7(%struct.Foo* nocapture %a, %struct.Foo* nocapture %b) nounwind {
; CHECK-NEXT: vld1.32 {d16, d17}, [r1]
; CHECK-NEXT: vst1.32 {d16, d17}, [r0]
; CHECK-NEXT: bx lr
+;
+; CHECK-T1-LABEL: t7:
+; CHECK-T1: @ %bb.0: @ %entry
+; CHECK-T1-NEXT: ldr r2, [r1, #12]
+; CHECK-T1-NEXT: str r2, [r0, #12]
+; CHECK-T1-NEXT: ldr r2, [r1, #8]
+; CHECK-T1-NEXT: str r2, [r0, #8]
+; CHECK-T1-NEXT: ldr r2, [r1, #4]
+; CHECK-T1-NEXT: str r2, [r0, #4]
+; CHECK-T1-NEXT: ldr r1, [r1]
+; CHECK-T1-NEXT: str r1, [r0]
+; CHECK-T1-NEXT: bx lr
entry:
%0 = bitcast %struct.Foo* %a to i8*
%1 = bitcast %struct.Foo* %b to i8*
@@ -165,5 +286,3 @@ entry:
declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture, i8* nocapture, i32, i1) nounwind
declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture, i64, i1) nounwind
-;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
-; CHECK-T1: {{.*}}
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