[PATCH] D134477: [isel] Lower vector interleave into unpck and perm
Simon Pilgrim via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Sat Sep 24 08:27:25 PDT 2022
RKSimon added inline comments.
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Comment at: llvm/lib/Target/X86/X86ISelLowering.cpp:17802
+ bool IsFirstHalf = IsInterleavingPattern(Mask, 0, 32);
+ bool IsSecondHalf = IsInterleavingPattern(Mask, 16, 48);
+ if (!IsFirstHalf && !IsSecondHalf)
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I'd probably replace these hard coded numbers with more general NumElts / NumEltsPerLane variables.
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Comment at: llvm/lib/Target/X86/X86ISelLowering.cpp:17841
+ DAG.ReplaceAllUsesWith(SecondHalf, &Perm2);
+ return Perm1;
+ }
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Why are the ReplaceAllUsesWith calls necessary? We usually just rely on combines / demandedelts to replace these.
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Comment at: llvm/lib/Target/X86/X86ISelLowering.cpp:18513
+ lowerShufflePairAsUNPCKAndPermute(DL, MVT::v32i8, V1, V2, Mask, DAG))
+ return V;
+
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I'm still not certain if we're better off trying to perform this in lowering or via shuffle combining or maybe combineConcatVectorOps?
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D134477/new/
https://reviews.llvm.org/D134477
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