[llvm] 0d58a8c - [RISCV] Merge half-intrinsics-strict.ll into zvh-half-intrinsics-strict.ll. NFC
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Fri Sep 23 16:42:36 PDT 2022
Author: Craig Topper
Date: 2022-09-23T16:37:47-07:00
New Revision: 0d58a8cd493ea742c28b4d7e684df947e66fe6e8
URL: https://github.com/llvm/llvm-project/commit/0d58a8cd493ea742c28b4d7e684df947e66fe6e8
DIFF: https://github.com/llvm/llvm-project/commit/0d58a8cd493ea742c28b4d7e684df947e66fe6e8.diff
LOG: [RISCV] Merge half-intrinsics-strict.ll into zvh-half-intrinsics-strict.ll. NFC
I had forgotten how we had the files partitioned.
Added:
Modified:
llvm/test/CodeGen/RISCV/zfh-half-intrinsics-strict.ll
Removed:
llvm/test/CodeGen/RISCV/half-intrinsics-strict.ll
################################################################################
diff --git a/llvm/test/CodeGen/RISCV/half-intrinsics-strict.ll b/llvm/test/CodeGen/RISCV/half-intrinsics-strict.ll
deleted file mode 100644
index 9c5d752d8135..000000000000
--- a/llvm/test/CodeGen/RISCV/half-intrinsics-strict.ll
+++ /dev/null
@@ -1,252 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+zfh \
-; RUN: -verify-machineinstrs -target-abi ilp32f | \
-; RUN: FileCheck -check-prefixes=CHECKIZFH,RV32IZFH %s
-; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+zfh \
-; RUN: -verify-machineinstrs -target-abi lp64f | \
-; RUN: FileCheck -check-prefixes=CHECKIZFH,RV64IZFH %s
-; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+d \
-; RUN: -mattr=+zfh -verify-machineinstrs -target-abi ilp32d | \
-; RUN: FileCheck -check-prefixes=CHECKIZFH,RV32IZFH %s
-; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+d \
-; RUN: -mattr=+zfh -verify-machineinstrs -target-abi lp64d | \
-; RUN: FileCheck -check-prefixes=CHECKIZFH,RV64IZFH %s
-
-declare half @llvm.experimental.constrained.sqrt.f16(half, metadata, metadata)
-
-define half @sqrt_f16(half %a) nounwind strictfp {
-; CHECKIZFH-LABEL: sqrt_f16:
-; CHECKIZFH: # %bb.0:
-; CHECKIZFH-NEXT: fsqrt.h fa0, fa0
-; CHECKIZFH-NEXT: ret
- %1 = call half @llvm.experimental.constrained.sqrt.f16(half %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
- ret half %1
-}
-
-declare half @llvm.experimental.constrained.floor.f16(half, metadata)
-
-define half @floor_f16(half %a) nounwind strictfp {
-; RV32IZFH-LABEL: floor_f16:
-; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: addi sp, sp, -16
-; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IZFH-NEXT: fcvt.s.h fa0, fa0
-; RV32IZFH-NEXT: call floorf at plt
-; RV32IZFH-NEXT: fcvt.h.s fa0, fa0
-; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; RV32IZFH-NEXT: addi sp, sp, 16
-; RV32IZFH-NEXT: ret
-;
-; RV64IZFH-LABEL: floor_f16:
-; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: addi sp, sp, -16
-; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; RV64IZFH-NEXT: fcvt.s.h fa0, fa0
-; RV64IZFH-NEXT: call floorf at plt
-; RV64IZFH-NEXT: fcvt.h.s fa0, fa0
-; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
-; RV64IZFH-NEXT: addi sp, sp, 16
-; RV64IZFH-NEXT: ret
- %1 = call half @llvm.experimental.constrained.floor.f16(half %a, metadata !"fpexcept.strict") strictfp
- ret half %1
-}
-
-declare half @llvm.experimental.constrained.ceil.f16(half, metadata)
-
-define half @ceil_f16(half %a) nounwind strictfp {
-; RV32IZFH-LABEL: ceil_f16:
-; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: addi sp, sp, -16
-; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IZFH-NEXT: fcvt.s.h fa0, fa0
-; RV32IZFH-NEXT: call ceilf at plt
-; RV32IZFH-NEXT: fcvt.h.s fa0, fa0
-; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; RV32IZFH-NEXT: addi sp, sp, 16
-; RV32IZFH-NEXT: ret
-;
-; RV64IZFH-LABEL: ceil_f16:
-; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: addi sp, sp, -16
-; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; RV64IZFH-NEXT: fcvt.s.h fa0, fa0
-; RV64IZFH-NEXT: call ceilf at plt
-; RV64IZFH-NEXT: fcvt.h.s fa0, fa0
-; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
-; RV64IZFH-NEXT: addi sp, sp, 16
-; RV64IZFH-NEXT: ret
- %1 = call half @llvm.experimental.constrained.ceil.f16(half %a, metadata !"fpexcept.strict") strictfp
- ret half %1
-}
-
-declare half @llvm.experimental.constrained.trunc.f16(half, metadata)
-
-define half @trunc_f16(half %a) nounwind strictfp {
-; RV32IZFH-LABEL: trunc_f16:
-; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: addi sp, sp, -16
-; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IZFH-NEXT: fcvt.s.h fa0, fa0
-; RV32IZFH-NEXT: call truncf at plt
-; RV32IZFH-NEXT: fcvt.h.s fa0, fa0
-; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; RV32IZFH-NEXT: addi sp, sp, 16
-; RV32IZFH-NEXT: ret
-;
-; RV64IZFH-LABEL: trunc_f16:
-; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: addi sp, sp, -16
-; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; RV64IZFH-NEXT: fcvt.s.h fa0, fa0
-; RV64IZFH-NEXT: call truncf at plt
-; RV64IZFH-NEXT: fcvt.h.s fa0, fa0
-; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
-; RV64IZFH-NEXT: addi sp, sp, 16
-; RV64IZFH-NEXT: ret
- %1 = call half @llvm.experimental.constrained.trunc.f16(half %a, metadata !"fpexcept.strict") strictfp
- ret half %1
-}
-
-declare half @llvm.experimental.constrained.rint.f16(half, metadata, metadata)
-
-define half @rint_f16(half %a) nounwind strictfp {
-; RV32IZFH-LABEL: rint_f16:
-; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: addi sp, sp, -16
-; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IZFH-NEXT: fcvt.s.h fa0, fa0
-; RV32IZFH-NEXT: call rintf at plt
-; RV32IZFH-NEXT: fcvt.h.s fa0, fa0
-; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; RV32IZFH-NEXT: addi sp, sp, 16
-; RV32IZFH-NEXT: ret
-;
-; RV64IZFH-LABEL: rint_f16:
-; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: addi sp, sp, -16
-; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; RV64IZFH-NEXT: fcvt.s.h fa0, fa0
-; RV64IZFH-NEXT: call rintf at plt
-; RV64IZFH-NEXT: fcvt.h.s fa0, fa0
-; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
-; RV64IZFH-NEXT: addi sp, sp, 16
-; RV64IZFH-NEXT: ret
- %1 = call half @llvm.experimental.constrained.rint.f16(half %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
- ret half %1
-}
-
-declare half @llvm.experimental.constrained.nearbyint.f16(half, metadata, metadata)
-
-define half @nearbyint_f16(half %a) nounwind strictfp {
-; RV32IZFH-LABEL: nearbyint_f16:
-; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: addi sp, sp, -16
-; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IZFH-NEXT: fcvt.s.h fa0, fa0
-; RV32IZFH-NEXT: call nearbyintf at plt
-; RV32IZFH-NEXT: fcvt.h.s fa0, fa0
-; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; RV32IZFH-NEXT: addi sp, sp, 16
-; RV32IZFH-NEXT: ret
-;
-; RV64IZFH-LABEL: nearbyint_f16:
-; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: addi sp, sp, -16
-; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; RV64IZFH-NEXT: fcvt.s.h fa0, fa0
-; RV64IZFH-NEXT: call nearbyintf at plt
-; RV64IZFH-NEXT: fcvt.h.s fa0, fa0
-; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
-; RV64IZFH-NEXT: addi sp, sp, 16
-; RV64IZFH-NEXT: ret
- %1 = call half @llvm.experimental.constrained.nearbyint.f16(half %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
- ret half %1
-}
-
-declare half @llvm.experimental.constrained.round.f16(half, metadata)
-
-define half @round_f16(half %a) nounwind strictfp {
-; RV32IZFH-LABEL: round_f16:
-; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: addi sp, sp, -16
-; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IZFH-NEXT: fcvt.s.h fa0, fa0
-; RV32IZFH-NEXT: call roundf at plt
-; RV32IZFH-NEXT: fcvt.h.s fa0, fa0
-; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; RV32IZFH-NEXT: addi sp, sp, 16
-; RV32IZFH-NEXT: ret
-;
-; RV64IZFH-LABEL: round_f16:
-; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: addi sp, sp, -16
-; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; RV64IZFH-NEXT: fcvt.s.h fa0, fa0
-; RV64IZFH-NEXT: call roundf at plt
-; RV64IZFH-NEXT: fcvt.h.s fa0, fa0
-; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
-; RV64IZFH-NEXT: addi sp, sp, 16
-; RV64IZFH-NEXT: ret
- %1 = call half @llvm.experimental.constrained.round.f16(half %a, metadata !"fpexcept.strict") strictfp
- ret half %1
-}
-
-declare half @llvm.experimental.constrained.roundeven.f16(half, metadata)
-
-define half @roundeven_f16(half %a) nounwind strictfp {
-; RV32IZFH-LABEL: roundeven_f16:
-; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: addi sp, sp, -16
-; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IZFH-NEXT: fcvt.s.h fa0, fa0
-; RV32IZFH-NEXT: call roundevenf at plt
-; RV32IZFH-NEXT: fcvt.h.s fa0, fa0
-; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; RV32IZFH-NEXT: addi sp, sp, 16
-; RV32IZFH-NEXT: ret
-;
-; RV64IZFH-LABEL: roundeven_f16:
-; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: addi sp, sp, -16
-; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; RV64IZFH-NEXT: fcvt.s.h fa0, fa0
-; RV64IZFH-NEXT: call roundevenf at plt
-; RV64IZFH-NEXT: fcvt.h.s fa0, fa0
-; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
-; RV64IZFH-NEXT: addi sp, sp, 16
-; RV64IZFH-NEXT: ret
- %1 = call half @llvm.experimental.constrained.roundeven.f16(half %a, metadata !"fpexcept.strict") strictfp
- ret half %1
-}
-
-declare iXLen @llvm.experimental.constrained.lrint.iXLen.f16(half, metadata, metadata)
-
-define iXLen @lrint_f16(half %a) nounwind strictfp {
-; RV32IZFH-LABEL: lrint_f16:
-; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: fcvt.w.h a0, fa0
-; RV32IZFH-NEXT: ret
-;
-; RV64IZFH-LABEL: lrint_f16:
-; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: fcvt.l.h a0, fa0
-; RV64IZFH-NEXT: ret
- %1 = call iXLen @llvm.experimental.constrained.lrint.iXLen.f16(half %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
- ret iXLen %1
-}
-
-declare iXLen @llvm.experimental.constrained.lround.iXLen.f16(half, metadata)
-
-define iXLen @lround_f16(half %a) nounwind strictfp {
-; RV32IZFH-LABEL: lround_f16:
-; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: fcvt.w.h a0, fa0, rmm
-; RV32IZFH-NEXT: ret
-;
-; RV64IZFH-LABEL: lround_f16:
-; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: fcvt.l.h a0, fa0, rmm
-; RV64IZFH-NEXT: ret
- %1 = call iXLen @llvm.experimental.constrained.lround.iXLen.f16(half %a, metadata !"fpexcept.strict") strictfp
- ret iXLen %1
-}
diff --git a/llvm/test/CodeGen/RISCV/zfh-half-intrinsics-strict.ll b/llvm/test/CodeGen/RISCV/zfh-half-intrinsics-strict.ll
index 42fc5a263d0a..b93d9cc34ee1 100644
--- a/llvm/test/CodeGen/RISCV/zfh-half-intrinsics-strict.ll
+++ b/llvm/test/CodeGen/RISCV/zfh-half-intrinsics-strict.ll
@@ -7,10 +7,222 @@
; RUN: | FileCheck -check-prefix=RV64IZFH %s
; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+d \
; RUN: -mattr=+zfh -verify-machineinstrs -target-abi ilp32d \
-; RUN: -disable-strictnode-mutation | FileCheck -check-prefix=RV32IDZFH %s
+; RUN: -disable-strictnode-mutation | FileCheck -check-prefix=RV32IZFH %s
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+d \
; RUN: -mattr=+zfh -verify-machineinstrs -target-abi lp64d \
-; RUN: -disable-strictnode-mutation | FileCheck -check-prefix=RV64IDZFH %s
+; RUN: -disable-strictnode-mutation | FileCheck -check-prefix=RV64IZFH %s
+
+declare half @llvm.experimental.constrained.sqrt.f16(half, metadata, metadata)
+
+define half @sqrt_f16(half %a) nounwind strictfp {
+; RV32IZFH-LABEL: sqrt_f16:
+; RV32IZFH: # %bb.0:
+; RV32IZFH-NEXT: fsqrt.h fa0, fa0
+; RV32IZFH-NEXT: ret
+;
+; RV64IZFH-LABEL: sqrt_f16:
+; RV64IZFH: # %bb.0:
+; RV64IZFH-NEXT: fsqrt.h fa0, fa0
+; RV64IZFH-NEXT: ret
+ %1 = call half @llvm.experimental.constrained.sqrt.f16(half %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
+ ret half %1
+}
+
+declare half @llvm.experimental.constrained.floor.f16(half, metadata)
+
+define half @floor_f16(half %a) nounwind strictfp {
+; RV32IZFH-LABEL: floor_f16:
+; RV32IZFH: # %bb.0:
+; RV32IZFH-NEXT: addi sp, sp, -16
+; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFH-NEXT: fcvt.s.h fa0, fa0
+; RV32IZFH-NEXT: call floorf at plt
+; RV32IZFH-NEXT: fcvt.h.s fa0, fa0
+; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZFH-NEXT: addi sp, sp, 16
+; RV32IZFH-NEXT: ret
+;
+; RV64IZFH-LABEL: floor_f16:
+; RV64IZFH: # %bb.0:
+; RV64IZFH-NEXT: addi sp, sp, -16
+; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZFH-NEXT: fcvt.s.h fa0, fa0
+; RV64IZFH-NEXT: call floorf at plt
+; RV64IZFH-NEXT: fcvt.h.s fa0, fa0
+; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IZFH-NEXT: addi sp, sp, 16
+; RV64IZFH-NEXT: ret
+ %1 = call half @llvm.experimental.constrained.floor.f16(half %a, metadata !"fpexcept.strict") strictfp
+ ret half %1
+}
+
+declare half @llvm.experimental.constrained.ceil.f16(half, metadata)
+
+define half @ceil_f16(half %a) nounwind strictfp {
+; RV32IZFH-LABEL: ceil_f16:
+; RV32IZFH: # %bb.0:
+; RV32IZFH-NEXT: addi sp, sp, -16
+; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFH-NEXT: fcvt.s.h fa0, fa0
+; RV32IZFH-NEXT: call ceilf at plt
+; RV32IZFH-NEXT: fcvt.h.s fa0, fa0
+; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZFH-NEXT: addi sp, sp, 16
+; RV32IZFH-NEXT: ret
+;
+; RV64IZFH-LABEL: ceil_f16:
+; RV64IZFH: # %bb.0:
+; RV64IZFH-NEXT: addi sp, sp, -16
+; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZFH-NEXT: fcvt.s.h fa0, fa0
+; RV64IZFH-NEXT: call ceilf at plt
+; RV64IZFH-NEXT: fcvt.h.s fa0, fa0
+; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IZFH-NEXT: addi sp, sp, 16
+; RV64IZFH-NEXT: ret
+ %1 = call half @llvm.experimental.constrained.ceil.f16(half %a, metadata !"fpexcept.strict") strictfp
+ ret half %1
+}
+
+declare half @llvm.experimental.constrained.trunc.f16(half, metadata)
+
+define half @trunc_f16(half %a) nounwind strictfp {
+; RV32IZFH-LABEL: trunc_f16:
+; RV32IZFH: # %bb.0:
+; RV32IZFH-NEXT: addi sp, sp, -16
+; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFH-NEXT: fcvt.s.h fa0, fa0
+; RV32IZFH-NEXT: call truncf at plt
+; RV32IZFH-NEXT: fcvt.h.s fa0, fa0
+; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZFH-NEXT: addi sp, sp, 16
+; RV32IZFH-NEXT: ret
+;
+; RV64IZFH-LABEL: trunc_f16:
+; RV64IZFH: # %bb.0:
+; RV64IZFH-NEXT: addi sp, sp, -16
+; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZFH-NEXT: fcvt.s.h fa0, fa0
+; RV64IZFH-NEXT: call truncf at plt
+; RV64IZFH-NEXT: fcvt.h.s fa0, fa0
+; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IZFH-NEXT: addi sp, sp, 16
+; RV64IZFH-NEXT: ret
+ %1 = call half @llvm.experimental.constrained.trunc.f16(half %a, metadata !"fpexcept.strict") strictfp
+ ret half %1
+}
+
+declare half @llvm.experimental.constrained.rint.f16(half, metadata, metadata)
+
+define half @rint_f16(half %a) nounwind strictfp {
+; RV32IZFH-LABEL: rint_f16:
+; RV32IZFH: # %bb.0:
+; RV32IZFH-NEXT: addi sp, sp, -16
+; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFH-NEXT: fcvt.s.h fa0, fa0
+; RV32IZFH-NEXT: call rintf at plt
+; RV32IZFH-NEXT: fcvt.h.s fa0, fa0
+; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZFH-NEXT: addi sp, sp, 16
+; RV32IZFH-NEXT: ret
+;
+; RV64IZFH-LABEL: rint_f16:
+; RV64IZFH: # %bb.0:
+; RV64IZFH-NEXT: addi sp, sp, -16
+; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZFH-NEXT: fcvt.s.h fa0, fa0
+; RV64IZFH-NEXT: call rintf at plt
+; RV64IZFH-NEXT: fcvt.h.s fa0, fa0
+; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IZFH-NEXT: addi sp, sp, 16
+; RV64IZFH-NEXT: ret
+ %1 = call half @llvm.experimental.constrained.rint.f16(half %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
+ ret half %1
+}
+
+declare half @llvm.experimental.constrained.nearbyint.f16(half, metadata, metadata)
+
+define half @nearbyint_f16(half %a) nounwind strictfp {
+; RV32IZFH-LABEL: nearbyint_f16:
+; RV32IZFH: # %bb.0:
+; RV32IZFH-NEXT: addi sp, sp, -16
+; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFH-NEXT: fcvt.s.h fa0, fa0
+; RV32IZFH-NEXT: call nearbyintf at plt
+; RV32IZFH-NEXT: fcvt.h.s fa0, fa0
+; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZFH-NEXT: addi sp, sp, 16
+; RV32IZFH-NEXT: ret
+;
+; RV64IZFH-LABEL: nearbyint_f16:
+; RV64IZFH: # %bb.0:
+; RV64IZFH-NEXT: addi sp, sp, -16
+; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZFH-NEXT: fcvt.s.h fa0, fa0
+; RV64IZFH-NEXT: call nearbyintf at plt
+; RV64IZFH-NEXT: fcvt.h.s fa0, fa0
+; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IZFH-NEXT: addi sp, sp, 16
+; RV64IZFH-NEXT: ret
+ %1 = call half @llvm.experimental.constrained.nearbyint.f16(half %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
+ ret half %1
+}
+
+declare half @llvm.experimental.constrained.round.f16(half, metadata)
+
+define half @round_f16(half %a) nounwind strictfp {
+; RV32IZFH-LABEL: round_f16:
+; RV32IZFH: # %bb.0:
+; RV32IZFH-NEXT: addi sp, sp, -16
+; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFH-NEXT: fcvt.s.h fa0, fa0
+; RV32IZFH-NEXT: call roundf at plt
+; RV32IZFH-NEXT: fcvt.h.s fa0, fa0
+; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZFH-NEXT: addi sp, sp, 16
+; RV32IZFH-NEXT: ret
+;
+; RV64IZFH-LABEL: round_f16:
+; RV64IZFH: # %bb.0:
+; RV64IZFH-NEXT: addi sp, sp, -16
+; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZFH-NEXT: fcvt.s.h fa0, fa0
+; RV64IZFH-NEXT: call roundf at plt
+; RV64IZFH-NEXT: fcvt.h.s fa0, fa0
+; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IZFH-NEXT: addi sp, sp, 16
+; RV64IZFH-NEXT: ret
+ %1 = call half @llvm.experimental.constrained.round.f16(half %a, metadata !"fpexcept.strict") strictfp
+ ret half %1
+}
+
+declare half @llvm.experimental.constrained.roundeven.f16(half, metadata)
+
+define half @roundeven_f16(half %a) nounwind strictfp {
+; RV32IZFH-LABEL: roundeven_f16:
+; RV32IZFH: # %bb.0:
+; RV32IZFH-NEXT: addi sp, sp, -16
+; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFH-NEXT: fcvt.s.h fa0, fa0
+; RV32IZFH-NEXT: call roundevenf at plt
+; RV32IZFH-NEXT: fcvt.h.s fa0, fa0
+; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZFH-NEXT: addi sp, sp, 16
+; RV32IZFH-NEXT: ret
+;
+; RV64IZFH-LABEL: roundeven_f16:
+; RV64IZFH: # %bb.0:
+; RV64IZFH-NEXT: addi sp, sp, -16
+; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZFH-NEXT: fcvt.s.h fa0, fa0
+; RV64IZFH-NEXT: call roundevenf at plt
+; RV64IZFH-NEXT: fcvt.h.s fa0, fa0
+; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IZFH-NEXT: addi sp, sp, 16
+; RV64IZFH-NEXT: ret
+ %1 = call half @llvm.experimental.constrained.roundeven.f16(half %a, metadata !"fpexcept.strict") strictfp
+ ret half %1
+}
declare iXLen @llvm.experimental.constrained.lrint.iXLen.f16(half, metadata, metadata)
@@ -24,16 +236,6 @@ define iXLen @lrint_f16(half %a) nounwind strictfp {
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: fcvt.l.h a0, fa0
; RV64IZFH-NEXT: ret
-;
-; RV32IDZFH-LABEL: lrint_f16:
-; RV32IDZFH: # %bb.0:
-; RV32IDZFH-NEXT: fcvt.w.h a0, fa0
-; RV32IDZFH-NEXT: ret
-;
-; RV64IDZFH-LABEL: lrint_f16:
-; RV64IDZFH: # %bb.0:
-; RV64IDZFH-NEXT: fcvt.l.h a0, fa0
-; RV64IDZFH-NEXT: ret
%1 = call iXLen @llvm.experimental.constrained.lrint.iXLen.f16(half %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
ret iXLen %1
}
@@ -50,16 +252,6 @@ define iXLen @lround_f16(half %a) nounwind strictfp {
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: fcvt.l.h a0, fa0, rmm
; RV64IZFH-NEXT: ret
-;
-; RV32IDZFH-LABEL: lround_f16:
-; RV32IDZFH: # %bb.0:
-; RV32IDZFH-NEXT: fcvt.w.h a0, fa0, rmm
-; RV32IDZFH-NEXT: ret
-;
-; RV64IDZFH-LABEL: lround_f16:
-; RV64IDZFH: # %bb.0:
-; RV64IDZFH-NEXT: fcvt.l.h a0, fa0, rmm
-; RV64IDZFH-NEXT: ret
%1 = call iXLen @llvm.experimental.constrained.lround.iXLen.f16(half %a, metadata !"fpexcept.strict") strictfp
ret iXLen %1
}
More information about the llvm-commits
mailing list