[llvm] f466838 - [RISCV] Simplify check-prefixes in half-intrinsics.ll. NFC
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Fri Sep 23 13:26:35 PDT 2022
Author: Craig Topper
Date: 2022-09-23T13:26:07-07:00
New Revision: f46683851195777b0a28b9fb9952464f23bbc1e7
URL: https://github.com/llvm/llvm-project/commit/f46683851195777b0a28b9fb9952464f23bbc1e7
DIFF: https://github.com/llvm/llvm-project/commit/f46683851195777b0a28b9fb9952464f23bbc1e7.diff
LOG: [RISCV] Simplify check-prefixes in half-intrinsics.ll. NFC
Added:
Modified:
llvm/test/CodeGen/RISCV/half-intrinsics.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/RISCV/half-intrinsics.ll b/llvm/test/CodeGen/RISCV/half-intrinsics.ll
index caa9f37083246..82d81d6006aa1 100644
--- a/llvm/test/CodeGen/RISCV/half-intrinsics.ll
+++ b/llvm/test/CodeGen/RISCV/half-intrinsics.ll
@@ -1,16 +1,16 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+zfh \
; RUN: -verify-machineinstrs -target-abi ilp32f | \
-; RUN: FileCheck -check-prefixes=CHECKIZFH,RV32IZFH %s
+; RUN: FileCheck -check-prefixes=CHECKIZFH,RV32IZFH,RV32IFZFH %s
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+zfh \
; RUN: -verify-machineinstrs -target-abi lp64f | \
-; RUN: FileCheck -check-prefixes=CHECKIZFH,RV64IZFH %s
+; RUN: FileCheck -check-prefixes=CHECKIZFH,RV64IZFH,RV64IFZFH %s
; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+d \
; RUN: -mattr=+zfh -verify-machineinstrs -target-abi ilp32d | \
-; RUN: FileCheck -check-prefix=RV32IDZFH %s
+; RUN: FileCheck -check-prefixes=CHECKIZFH,RV32IZFH,RV32IDZFH %s
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+d \
; RUN: -mattr=+zfh -verify-machineinstrs -target-abi lp64d | \
-; RUN: FileCheck -check-prefix=RV64IDZFH %s
+; RUN: FileCheck -check-prefixes=CHECKIZFH,RV64IZFH,RV64IDZFH %s
; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 \
; RUN: -verify-machineinstrs | \
; RUN: FileCheck -check-prefix=RV32I %s
@@ -26,16 +26,6 @@ define half @sqrt_f16(half %a) nounwind {
; CHECKIZFH-NEXT: fsqrt.h fa0, fa0
; CHECKIZFH-NEXT: ret
;
-; RV32IDZFH-LABEL: sqrt_f16:
-; RV32IDZFH: # %bb.0:
-; RV32IDZFH-NEXT: fsqrt.h fa0, fa0
-; RV32IDZFH-NEXT: ret
-;
-; RV64IDZFH-LABEL: sqrt_f16:
-; RV64IDZFH: # %bb.0:
-; RV64IDZFH-NEXT: fsqrt.h fa0, fa0
-; RV64IDZFH-NEXT: ret
-;
; RV32I-LABEL: sqrt_f16:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
@@ -91,29 +81,6 @@ define half @powi_f16(half %a, i32 %b) nounwind {
; RV64IZFH-NEXT: addi sp, sp, 16
; RV64IZFH-NEXT: ret
;
-; RV32IDZFH-LABEL: powi_f16:
-; RV32IDZFH: # %bb.0:
-; RV32IDZFH-NEXT: addi sp, sp, -16
-; RV32IDZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IDZFH-NEXT: fcvt.s.h fa0, fa0
-; RV32IDZFH-NEXT: call __powisf2 at plt
-; RV32IDZFH-NEXT: fcvt.h.s fa0, fa0
-; RV32IDZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; RV32IDZFH-NEXT: addi sp, sp, 16
-; RV32IDZFH-NEXT: ret
-;
-; RV64IDZFH-LABEL: powi_f16:
-; RV64IDZFH: # %bb.0:
-; RV64IDZFH-NEXT: addi sp, sp, -16
-; RV64IDZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; RV64IDZFH-NEXT: fcvt.s.h fa0, fa0
-; RV64IDZFH-NEXT: sext.w a0, a0
-; RV64IDZFH-NEXT: call __powisf2 at plt
-; RV64IDZFH-NEXT: fcvt.h.s fa0, fa0
-; RV64IDZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
-; RV64IDZFH-NEXT: addi sp, sp, 16
-; RV64IDZFH-NEXT: ret
-;
; RV32I-LABEL: powi_f16:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
@@ -176,28 +143,6 @@ define half @sin_f16(half %a) nounwind {
; RV64IZFH-NEXT: addi sp, sp, 16
; RV64IZFH-NEXT: ret
;
-; RV32IDZFH-LABEL: sin_f16:
-; RV32IDZFH: # %bb.0:
-; RV32IDZFH-NEXT: addi sp, sp, -16
-; RV32IDZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IDZFH-NEXT: fcvt.s.h fa0, fa0
-; RV32IDZFH-NEXT: call sinf at plt
-; RV32IDZFH-NEXT: fcvt.h.s fa0, fa0
-; RV32IDZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; RV32IDZFH-NEXT: addi sp, sp, 16
-; RV32IDZFH-NEXT: ret
-;
-; RV64IDZFH-LABEL: sin_f16:
-; RV64IDZFH: # %bb.0:
-; RV64IDZFH-NEXT: addi sp, sp, -16
-; RV64IDZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; RV64IDZFH-NEXT: fcvt.s.h fa0, fa0
-; RV64IDZFH-NEXT: call sinf at plt
-; RV64IDZFH-NEXT: fcvt.h.s fa0, fa0
-; RV64IDZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
-; RV64IDZFH-NEXT: addi sp, sp, 16
-; RV64IDZFH-NEXT: ret
-;
; RV32I-LABEL: sin_f16:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
@@ -252,28 +197,6 @@ define half @cos_f16(half %a) nounwind {
; RV64IZFH-NEXT: addi sp, sp, 16
; RV64IZFH-NEXT: ret
;
-; RV32IDZFH-LABEL: cos_f16:
-; RV32IDZFH: # %bb.0:
-; RV32IDZFH-NEXT: addi sp, sp, -16
-; RV32IDZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IDZFH-NEXT: fcvt.s.h fa0, fa0
-; RV32IDZFH-NEXT: call cosf at plt
-; RV32IDZFH-NEXT: fcvt.h.s fa0, fa0
-; RV32IDZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; RV32IDZFH-NEXT: addi sp, sp, 16
-; RV32IDZFH-NEXT: ret
-;
-; RV64IDZFH-LABEL: cos_f16:
-; RV64IDZFH: # %bb.0:
-; RV64IDZFH-NEXT: addi sp, sp, -16
-; RV64IDZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; RV64IDZFH-NEXT: fcvt.s.h fa0, fa0
-; RV64IDZFH-NEXT: call cosf at plt
-; RV64IDZFH-NEXT: fcvt.h.s fa0, fa0
-; RV64IDZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
-; RV64IDZFH-NEXT: addi sp, sp, 16
-; RV64IDZFH-NEXT: ret
-;
; RV32I-LABEL: cos_f16:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
@@ -305,45 +228,45 @@ define half @cos_f16(half %a) nounwind {
; The sin+cos combination results in an FSINCOS SelectionDAG node.
define half @sincos_f16(half %a) nounwind {
-; RV32IZFH-LABEL: sincos_f16:
-; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: addi sp, sp, -16
-; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IZFH-NEXT: fsw fs0, 8(sp) # 4-byte Folded Spill
-; RV32IZFH-NEXT: fsw fs1, 4(sp) # 4-byte Folded Spill
-; RV32IZFH-NEXT: fcvt.s.h fs0, fa0
-; RV32IZFH-NEXT: fmv.s fa0, fs0
-; RV32IZFH-NEXT: call sinf at plt
-; RV32IZFH-NEXT: fcvt.h.s fs1, fa0
-; RV32IZFH-NEXT: fmv.s fa0, fs0
-; RV32IZFH-NEXT: call cosf at plt
-; RV32IZFH-NEXT: fcvt.h.s ft0, fa0
-; RV32IZFH-NEXT: fadd.h fa0, fs1, ft0
-; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; RV32IZFH-NEXT: flw fs0, 8(sp) # 4-byte Folded Reload
-; RV32IZFH-NEXT: flw fs1, 4(sp) # 4-byte Folded Reload
-; RV32IZFH-NEXT: addi sp, sp, 16
-; RV32IZFH-NEXT: ret
-;
-; RV64IZFH-LABEL: sincos_f16:
-; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: addi sp, sp, -16
-; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; RV64IZFH-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill
-; RV64IZFH-NEXT: fsw fs1, 0(sp) # 4-byte Folded Spill
-; RV64IZFH-NEXT: fcvt.s.h fs0, fa0
-; RV64IZFH-NEXT: fmv.s fa0, fs0
-; RV64IZFH-NEXT: call sinf at plt
-; RV64IZFH-NEXT: fcvt.h.s fs1, fa0
-; RV64IZFH-NEXT: fmv.s fa0, fs0
-; RV64IZFH-NEXT: call cosf at plt
-; RV64IZFH-NEXT: fcvt.h.s ft0, fa0
-; RV64IZFH-NEXT: fadd.h fa0, fs1, ft0
-; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
-; RV64IZFH-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload
-; RV64IZFH-NEXT: flw fs1, 0(sp) # 4-byte Folded Reload
-; RV64IZFH-NEXT: addi sp, sp, 16
-; RV64IZFH-NEXT: ret
+; RV32IFZFH-LABEL: sincos_f16:
+; RV32IFZFH: # %bb.0:
+; RV32IFZFH-NEXT: addi sp, sp, -16
+; RV32IFZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IFZFH-NEXT: fsw fs0, 8(sp) # 4-byte Folded Spill
+; RV32IFZFH-NEXT: fsw fs1, 4(sp) # 4-byte Folded Spill
+; RV32IFZFH-NEXT: fcvt.s.h fs0, fa0
+; RV32IFZFH-NEXT: fmv.s fa0, fs0
+; RV32IFZFH-NEXT: call sinf at plt
+; RV32IFZFH-NEXT: fcvt.h.s fs1, fa0
+; RV32IFZFH-NEXT: fmv.s fa0, fs0
+; RV32IFZFH-NEXT: call cosf at plt
+; RV32IFZFH-NEXT: fcvt.h.s ft0, fa0
+; RV32IFZFH-NEXT: fadd.h fa0, fs1, ft0
+; RV32IFZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IFZFH-NEXT: flw fs0, 8(sp) # 4-byte Folded Reload
+; RV32IFZFH-NEXT: flw fs1, 4(sp) # 4-byte Folded Reload
+; RV32IFZFH-NEXT: addi sp, sp, 16
+; RV32IFZFH-NEXT: ret
+;
+; RV64IFZFH-LABEL: sincos_f16:
+; RV64IFZFH: # %bb.0:
+; RV64IFZFH-NEXT: addi sp, sp, -16
+; RV64IFZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IFZFH-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill
+; RV64IFZFH-NEXT: fsw fs1, 0(sp) # 4-byte Folded Spill
+; RV64IFZFH-NEXT: fcvt.s.h fs0, fa0
+; RV64IFZFH-NEXT: fmv.s fa0, fs0
+; RV64IFZFH-NEXT: call sinf at plt
+; RV64IFZFH-NEXT: fcvt.h.s fs1, fa0
+; RV64IFZFH-NEXT: fmv.s fa0, fs0
+; RV64IFZFH-NEXT: call cosf at plt
+; RV64IFZFH-NEXT: fcvt.h.s ft0, fa0
+; RV64IFZFH-NEXT: fadd.h fa0, fs1, ft0
+; RV64IFZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IFZFH-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload
+; RV64IFZFH-NEXT: flw fs1, 0(sp) # 4-byte Folded Reload
+; RV64IFZFH-NEXT: addi sp, sp, 16
+; RV64IFZFH-NEXT: ret
;
; RV32IDZFH-LABEL: sincos_f16:
; RV32IDZFH: # %bb.0:
@@ -487,30 +410,6 @@ define half @pow_f16(half %a, half %b) nounwind {
; RV64IZFH-NEXT: addi sp, sp, 16
; RV64IZFH-NEXT: ret
;
-; RV32IDZFH-LABEL: pow_f16:
-; RV32IDZFH: # %bb.0:
-; RV32IDZFH-NEXT: addi sp, sp, -16
-; RV32IDZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IDZFH-NEXT: fcvt.s.h fa0, fa0
-; RV32IDZFH-NEXT: fcvt.s.h fa1, fa1
-; RV32IDZFH-NEXT: call powf at plt
-; RV32IDZFH-NEXT: fcvt.h.s fa0, fa0
-; RV32IDZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; RV32IDZFH-NEXT: addi sp, sp, 16
-; RV32IDZFH-NEXT: ret
-;
-; RV64IDZFH-LABEL: pow_f16:
-; RV64IDZFH: # %bb.0:
-; RV64IDZFH-NEXT: addi sp, sp, -16
-; RV64IDZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; RV64IDZFH-NEXT: fcvt.s.h fa0, fa0
-; RV64IDZFH-NEXT: fcvt.s.h fa1, fa1
-; RV64IDZFH-NEXT: call powf at plt
-; RV64IDZFH-NEXT: fcvt.h.s fa0, fa0
-; RV64IDZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
-; RV64IDZFH-NEXT: addi sp, sp, 16
-; RV64IDZFH-NEXT: ret
-;
; RV32I-LABEL: pow_f16:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
@@ -591,28 +490,6 @@ define half @exp_f16(half %a) nounwind {
; RV64IZFH-NEXT: addi sp, sp, 16
; RV64IZFH-NEXT: ret
;
-; RV32IDZFH-LABEL: exp_f16:
-; RV32IDZFH: # %bb.0:
-; RV32IDZFH-NEXT: addi sp, sp, -16
-; RV32IDZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IDZFH-NEXT: fcvt.s.h fa0, fa0
-; RV32IDZFH-NEXT: call expf at plt
-; RV32IDZFH-NEXT: fcvt.h.s fa0, fa0
-; RV32IDZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; RV32IDZFH-NEXT: addi sp, sp, 16
-; RV32IDZFH-NEXT: ret
-;
-; RV64IDZFH-LABEL: exp_f16:
-; RV64IDZFH: # %bb.0:
-; RV64IDZFH-NEXT: addi sp, sp, -16
-; RV64IDZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; RV64IDZFH-NEXT: fcvt.s.h fa0, fa0
-; RV64IDZFH-NEXT: call expf at plt
-; RV64IDZFH-NEXT: fcvt.h.s fa0, fa0
-; RV64IDZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
-; RV64IDZFH-NEXT: addi sp, sp, 16
-; RV64IDZFH-NEXT: ret
-;
; RV32I-LABEL: exp_f16:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
@@ -667,28 +544,6 @@ define half @exp2_f16(half %a) nounwind {
; RV64IZFH-NEXT: addi sp, sp, 16
; RV64IZFH-NEXT: ret
;
-; RV32IDZFH-LABEL: exp2_f16:
-; RV32IDZFH: # %bb.0:
-; RV32IDZFH-NEXT: addi sp, sp, -16
-; RV32IDZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IDZFH-NEXT: fcvt.s.h fa0, fa0
-; RV32IDZFH-NEXT: call exp2f at plt
-; RV32IDZFH-NEXT: fcvt.h.s fa0, fa0
-; RV32IDZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; RV32IDZFH-NEXT: addi sp, sp, 16
-; RV32IDZFH-NEXT: ret
-;
-; RV64IDZFH-LABEL: exp2_f16:
-; RV64IDZFH: # %bb.0:
-; RV64IDZFH-NEXT: addi sp, sp, -16
-; RV64IDZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; RV64IDZFH-NEXT: fcvt.s.h fa0, fa0
-; RV64IDZFH-NEXT: call exp2f at plt
-; RV64IDZFH-NEXT: fcvt.h.s fa0, fa0
-; RV64IDZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
-; RV64IDZFH-NEXT: addi sp, sp, 16
-; RV64IDZFH-NEXT: ret
-;
; RV32I-LABEL: exp2_f16:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
@@ -743,28 +598,6 @@ define half @log_f16(half %a) nounwind {
; RV64IZFH-NEXT: addi sp, sp, 16
; RV64IZFH-NEXT: ret
;
-; RV32IDZFH-LABEL: log_f16:
-; RV32IDZFH: # %bb.0:
-; RV32IDZFH-NEXT: addi sp, sp, -16
-; RV32IDZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IDZFH-NEXT: fcvt.s.h fa0, fa0
-; RV32IDZFH-NEXT: call logf at plt
-; RV32IDZFH-NEXT: fcvt.h.s fa0, fa0
-; RV32IDZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; RV32IDZFH-NEXT: addi sp, sp, 16
-; RV32IDZFH-NEXT: ret
-;
-; RV64IDZFH-LABEL: log_f16:
-; RV64IDZFH: # %bb.0:
-; RV64IDZFH-NEXT: addi sp, sp, -16
-; RV64IDZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; RV64IDZFH-NEXT: fcvt.s.h fa0, fa0
-; RV64IDZFH-NEXT: call logf at plt
-; RV64IDZFH-NEXT: fcvt.h.s fa0, fa0
-; RV64IDZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
-; RV64IDZFH-NEXT: addi sp, sp, 16
-; RV64IDZFH-NEXT: ret
-;
; RV32I-LABEL: log_f16:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
@@ -819,28 +652,6 @@ define half @log10_f16(half %a) nounwind {
; RV64IZFH-NEXT: addi sp, sp, 16
; RV64IZFH-NEXT: ret
;
-; RV32IDZFH-LABEL: log10_f16:
-; RV32IDZFH: # %bb.0:
-; RV32IDZFH-NEXT: addi sp, sp, -16
-; RV32IDZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IDZFH-NEXT: fcvt.s.h fa0, fa0
-; RV32IDZFH-NEXT: call log10f at plt
-; RV32IDZFH-NEXT: fcvt.h.s fa0, fa0
-; RV32IDZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; RV32IDZFH-NEXT: addi sp, sp, 16
-; RV32IDZFH-NEXT: ret
-;
-; RV64IDZFH-LABEL: log10_f16:
-; RV64IDZFH: # %bb.0:
-; RV64IDZFH-NEXT: addi sp, sp, -16
-; RV64IDZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; RV64IDZFH-NEXT: fcvt.s.h fa0, fa0
-; RV64IDZFH-NEXT: call log10f at plt
-; RV64IDZFH-NEXT: fcvt.h.s fa0, fa0
-; RV64IDZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
-; RV64IDZFH-NEXT: addi sp, sp, 16
-; RV64IDZFH-NEXT: ret
-;
; RV32I-LABEL: log10_f16:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
@@ -895,28 +706,6 @@ define half @log2_f16(half %a) nounwind {
; RV64IZFH-NEXT: addi sp, sp, 16
; RV64IZFH-NEXT: ret
;
-; RV32IDZFH-LABEL: log2_f16:
-; RV32IDZFH: # %bb.0:
-; RV32IDZFH-NEXT: addi sp, sp, -16
-; RV32IDZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IDZFH-NEXT: fcvt.s.h fa0, fa0
-; RV32IDZFH-NEXT: call log2f at plt
-; RV32IDZFH-NEXT: fcvt.h.s fa0, fa0
-; RV32IDZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; RV32IDZFH-NEXT: addi sp, sp, 16
-; RV32IDZFH-NEXT: ret
-;
-; RV64IDZFH-LABEL: log2_f16:
-; RV64IDZFH: # %bb.0:
-; RV64IDZFH-NEXT: addi sp, sp, -16
-; RV64IDZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; RV64IDZFH-NEXT: fcvt.s.h fa0, fa0
-; RV64IDZFH-NEXT: call log2f at plt
-; RV64IDZFH-NEXT: fcvt.h.s fa0, fa0
-; RV64IDZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
-; RV64IDZFH-NEXT: addi sp, sp, 16
-; RV64IDZFH-NEXT: ret
-;
; RV32I-LABEL: log2_f16:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
@@ -954,16 +743,6 @@ define half @fma_f16(half %a, half %b, half %c) nounwind {
; CHECKIZFH-NEXT: fmadd.h fa0, fa0, fa1, fa2
; CHECKIZFH-NEXT: ret
;
-; RV32IDZFH-LABEL: fma_f16:
-; RV32IDZFH: # %bb.0:
-; RV32IDZFH-NEXT: fmadd.h fa0, fa0, fa1, fa2
-; RV32IDZFH-NEXT: ret
-;
-; RV64IDZFH-LABEL: fma_f16:
-; RV64IDZFH: # %bb.0:
-; RV64IDZFH-NEXT: fmadd.h fa0, fa0, fa1, fa2
-; RV64IDZFH-NEXT: ret
-;
; RV32I-LABEL: fma_f16:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32
@@ -1041,16 +820,6 @@ define half @fmuladd_f16(half %a, half %b, half %c) nounwind {
; CHECKIZFH-NEXT: fmadd.h fa0, fa0, fa1, fa2
; CHECKIZFH-NEXT: ret
;
-; RV32IDZFH-LABEL: fmuladd_f16:
-; RV32IDZFH: # %bb.0:
-; RV32IDZFH-NEXT: fmadd.h fa0, fa0, fa1, fa2
-; RV32IDZFH-NEXT: ret
-;
-; RV64IDZFH-LABEL: fmuladd_f16:
-; RV64IDZFH: # %bb.0:
-; RV64IDZFH-NEXT: fmadd.h fa0, fa0, fa1, fa2
-; RV64IDZFH-NEXT: ret
-;
; RV32I-LABEL: fmuladd_f16:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32
@@ -1138,16 +907,6 @@ define half @fabs_f16(half %a) nounwind {
; CHECKIZFH-NEXT: fabs.h fa0, fa0
; CHECKIZFH-NEXT: ret
;
-; RV32IDZFH-LABEL: fabs_f16:
-; RV32IDZFH: # %bb.0:
-; RV32IDZFH-NEXT: fabs.h fa0, fa0
-; RV32IDZFH-NEXT: ret
-;
-; RV64IDZFH-LABEL: fabs_f16:
-; RV64IDZFH: # %bb.0:
-; RV64IDZFH-NEXT: fabs.h fa0, fa0
-; RV64IDZFH-NEXT: ret
-;
; RV32I-LABEL: fabs_f16:
; RV32I: # %bb.0:
; RV32I-NEXT: slli a0, a0, 17
@@ -1171,16 +930,6 @@ define half @minnum_f16(half %a, half %b) nounwind {
; CHECKIZFH-NEXT: fmin.h fa0, fa0, fa1
; CHECKIZFH-NEXT: ret
;
-; RV32IDZFH-LABEL: minnum_f16:
-; RV32IDZFH: # %bb.0:
-; RV32IDZFH-NEXT: fmin.h fa0, fa0, fa1
-; RV32IDZFH-NEXT: ret
-;
-; RV64IDZFH-LABEL: minnum_f16:
-; RV64IDZFH: # %bb.0:
-; RV64IDZFH-NEXT: fmin.h fa0, fa0, fa1
-; RV64IDZFH-NEXT: ret
-;
; RV32I-LABEL: minnum_f16:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
@@ -1244,16 +993,6 @@ define half @maxnum_f16(half %a, half %b) nounwind {
; CHECKIZFH-NEXT: fmax.h fa0, fa0, fa1
; CHECKIZFH-NEXT: ret
;
-; RV32IDZFH-LABEL: maxnum_f16:
-; RV32IDZFH: # %bb.0:
-; RV32IDZFH-NEXT: fmax.h fa0, fa0, fa1
-; RV32IDZFH-NEXT: ret
-;
-; RV64IDZFH-LABEL: maxnum_f16:
-; RV64IDZFH: # %bb.0:
-; RV64IDZFH-NEXT: fmax.h fa0, fa0, fa1
-; RV64IDZFH-NEXT: ret
-;
; RV32I-LABEL: maxnum_f16:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
@@ -1334,16 +1073,6 @@ define half @copysign_f16(half %a, half %b) nounwind {
; CHECKIZFH-NEXT: fsgnj.h fa0, fa0, fa1
; CHECKIZFH-NEXT: ret
;
-; RV32IDZFH-LABEL: copysign_f16:
-; RV32IDZFH: # %bb.0:
-; RV32IDZFH-NEXT: fsgnj.h fa0, fa0, fa1
-; RV32IDZFH-NEXT: ret
-;
-; RV64IDZFH-LABEL: copysign_f16:
-; RV64IDZFH: # %bb.0:
-; RV64IDZFH-NEXT: fsgnj.h fa0, fa0, fa1
-; RV64IDZFH-NEXT: ret
-;
; RV32I-LABEL: copysign_f16:
; RV32I: # %bb.0:
; RV32I-NEXT: lui a2, 1048568
@@ -1390,28 +1119,6 @@ define half @floor_f16(half %a) nounwind {
; RV64IZFH-NEXT: addi sp, sp, 16
; RV64IZFH-NEXT: ret
;
-; RV32IDZFH-LABEL: floor_f16:
-; RV32IDZFH: # %bb.0:
-; RV32IDZFH-NEXT: addi sp, sp, -16
-; RV32IDZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IDZFH-NEXT: fcvt.s.h fa0, fa0
-; RV32IDZFH-NEXT: call floorf at plt
-; RV32IDZFH-NEXT: fcvt.h.s fa0, fa0
-; RV32IDZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; RV32IDZFH-NEXT: addi sp, sp, 16
-; RV32IDZFH-NEXT: ret
-;
-; RV64IDZFH-LABEL: floor_f16:
-; RV64IDZFH: # %bb.0:
-; RV64IDZFH-NEXT: addi sp, sp, -16
-; RV64IDZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; RV64IDZFH-NEXT: fcvt.s.h fa0, fa0
-; RV64IDZFH-NEXT: call floorf at plt
-; RV64IDZFH-NEXT: fcvt.h.s fa0, fa0
-; RV64IDZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
-; RV64IDZFH-NEXT: addi sp, sp, 16
-; RV64IDZFH-NEXT: ret
-;
; RV32I-LABEL: floor_f16:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
@@ -1466,28 +1173,6 @@ define half @ceil_f16(half %a) nounwind {
; RV64IZFH-NEXT: addi sp, sp, 16
; RV64IZFH-NEXT: ret
;
-; RV32IDZFH-LABEL: ceil_f16:
-; RV32IDZFH: # %bb.0:
-; RV32IDZFH-NEXT: addi sp, sp, -16
-; RV32IDZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IDZFH-NEXT: fcvt.s.h fa0, fa0
-; RV32IDZFH-NEXT: call ceilf at plt
-; RV32IDZFH-NEXT: fcvt.h.s fa0, fa0
-; RV32IDZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; RV32IDZFH-NEXT: addi sp, sp, 16
-; RV32IDZFH-NEXT: ret
-;
-; RV64IDZFH-LABEL: ceil_f16:
-; RV64IDZFH: # %bb.0:
-; RV64IDZFH-NEXT: addi sp, sp, -16
-; RV64IDZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; RV64IDZFH-NEXT: fcvt.s.h fa0, fa0
-; RV64IDZFH-NEXT: call ceilf at plt
-; RV64IDZFH-NEXT: fcvt.h.s fa0, fa0
-; RV64IDZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
-; RV64IDZFH-NEXT: addi sp, sp, 16
-; RV64IDZFH-NEXT: ret
-;
; RV32I-LABEL: ceil_f16:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
@@ -1542,28 +1227,6 @@ define half @trunc_f16(half %a) nounwind {
; RV64IZFH-NEXT: addi sp, sp, 16
; RV64IZFH-NEXT: ret
;
-; RV32IDZFH-LABEL: trunc_f16:
-; RV32IDZFH: # %bb.0:
-; RV32IDZFH-NEXT: addi sp, sp, -16
-; RV32IDZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IDZFH-NEXT: fcvt.s.h fa0, fa0
-; RV32IDZFH-NEXT: call truncf at plt
-; RV32IDZFH-NEXT: fcvt.h.s fa0, fa0
-; RV32IDZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; RV32IDZFH-NEXT: addi sp, sp, 16
-; RV32IDZFH-NEXT: ret
-;
-; RV64IDZFH-LABEL: trunc_f16:
-; RV64IDZFH: # %bb.0:
-; RV64IDZFH-NEXT: addi sp, sp, -16
-; RV64IDZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; RV64IDZFH-NEXT: fcvt.s.h fa0, fa0
-; RV64IDZFH-NEXT: call truncf at plt
-; RV64IDZFH-NEXT: fcvt.h.s fa0, fa0
-; RV64IDZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
-; RV64IDZFH-NEXT: addi sp, sp, 16
-; RV64IDZFH-NEXT: ret
-;
; RV32I-LABEL: trunc_f16:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
@@ -1618,28 +1281,6 @@ define half @rint_f16(half %a) nounwind {
; RV64IZFH-NEXT: addi sp, sp, 16
; RV64IZFH-NEXT: ret
;
-; RV32IDZFH-LABEL: rint_f16:
-; RV32IDZFH: # %bb.0:
-; RV32IDZFH-NEXT: addi sp, sp, -16
-; RV32IDZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IDZFH-NEXT: fcvt.s.h fa0, fa0
-; RV32IDZFH-NEXT: call rintf at plt
-; RV32IDZFH-NEXT: fcvt.h.s fa0, fa0
-; RV32IDZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; RV32IDZFH-NEXT: addi sp, sp, 16
-; RV32IDZFH-NEXT: ret
-;
-; RV64IDZFH-LABEL: rint_f16:
-; RV64IDZFH: # %bb.0:
-; RV64IDZFH-NEXT: addi sp, sp, -16
-; RV64IDZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; RV64IDZFH-NEXT: fcvt.s.h fa0, fa0
-; RV64IDZFH-NEXT: call rintf at plt
-; RV64IDZFH-NEXT: fcvt.h.s fa0, fa0
-; RV64IDZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
-; RV64IDZFH-NEXT: addi sp, sp, 16
-; RV64IDZFH-NEXT: ret
-;
; RV32I-LABEL: rint_f16:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
@@ -1694,28 +1335,6 @@ define half @nearbyint_f16(half %a) nounwind {
; RV64IZFH-NEXT: addi sp, sp, 16
; RV64IZFH-NEXT: ret
;
-; RV32IDZFH-LABEL: nearbyint_f16:
-; RV32IDZFH: # %bb.0:
-; RV32IDZFH-NEXT: addi sp, sp, -16
-; RV32IDZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IDZFH-NEXT: fcvt.s.h fa0, fa0
-; RV32IDZFH-NEXT: call nearbyintf at plt
-; RV32IDZFH-NEXT: fcvt.h.s fa0, fa0
-; RV32IDZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; RV32IDZFH-NEXT: addi sp, sp, 16
-; RV32IDZFH-NEXT: ret
-;
-; RV64IDZFH-LABEL: nearbyint_f16:
-; RV64IDZFH: # %bb.0:
-; RV64IDZFH-NEXT: addi sp, sp, -16
-; RV64IDZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; RV64IDZFH-NEXT: fcvt.s.h fa0, fa0
-; RV64IDZFH-NEXT: call nearbyintf at plt
-; RV64IDZFH-NEXT: fcvt.h.s fa0, fa0
-; RV64IDZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
-; RV64IDZFH-NEXT: addi sp, sp, 16
-; RV64IDZFH-NEXT: ret
-;
; RV32I-LABEL: nearbyint_f16:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
@@ -1770,28 +1389,6 @@ define half @round_f16(half %a) nounwind {
; RV64IZFH-NEXT: addi sp, sp, 16
; RV64IZFH-NEXT: ret
;
-; RV32IDZFH-LABEL: round_f16:
-; RV32IDZFH: # %bb.0:
-; RV32IDZFH-NEXT: addi sp, sp, -16
-; RV32IDZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IDZFH-NEXT: fcvt.s.h fa0, fa0
-; RV32IDZFH-NEXT: call roundf at plt
-; RV32IDZFH-NEXT: fcvt.h.s fa0, fa0
-; RV32IDZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; RV32IDZFH-NEXT: addi sp, sp, 16
-; RV32IDZFH-NEXT: ret
-;
-; RV64IDZFH-LABEL: round_f16:
-; RV64IDZFH: # %bb.0:
-; RV64IDZFH-NEXT: addi sp, sp, -16
-; RV64IDZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; RV64IDZFH-NEXT: fcvt.s.h fa0, fa0
-; RV64IDZFH-NEXT: call roundf at plt
-; RV64IDZFH-NEXT: fcvt.h.s fa0, fa0
-; RV64IDZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
-; RV64IDZFH-NEXT: addi sp, sp, 16
-; RV64IDZFH-NEXT: ret
-;
; RV32I-LABEL: round_f16:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
@@ -1846,28 +1443,6 @@ define half @roundeven_f16(half %a) nounwind {
; RV64IZFH-NEXT: addi sp, sp, 16
; RV64IZFH-NEXT: ret
;
-; RV32IDZFH-LABEL: roundeven_f16:
-; RV32IDZFH: # %bb.0:
-; RV32IDZFH-NEXT: addi sp, sp, -16
-; RV32IDZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IDZFH-NEXT: fcvt.s.h fa0, fa0
-; RV32IDZFH-NEXT: call roundevenf at plt
-; RV32IDZFH-NEXT: fcvt.h.s fa0, fa0
-; RV32IDZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; RV32IDZFH-NEXT: addi sp, sp, 16
-; RV32IDZFH-NEXT: ret
-;
-; RV64IDZFH-LABEL: roundeven_f16:
-; RV64IDZFH: # %bb.0:
-; RV64IDZFH-NEXT: addi sp, sp, -16
-; RV64IDZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; RV64IDZFH-NEXT: fcvt.s.h fa0, fa0
-; RV64IDZFH-NEXT: call roundevenf at plt
-; RV64IDZFH-NEXT: fcvt.h.s fa0, fa0
-; RV64IDZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
-; RV64IDZFH-NEXT: addi sp, sp, 16
-; RV64IDZFH-NEXT: ret
-;
; RV32I-LABEL: roundeven_f16:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
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