[llvm] 954c1ed - [SLP] Adjust debug output for store vectorization failure

[Philip Reames via llvm-commits]

Author: Philip Reames
Date: 2022-09-23T09:58:15-07:00
New Revision: 954c1ed009d423ca9593ee63479a9394a23864fd

URL: https://github.com/llvm/llvm-project/commit/954c1ed009d423ca9593ee63479a9394a23864fd
DIFF: https://github.com/llvm/llvm-project/commit/954c1ed009d423ca9593ee63479a9394a23864fd.diff

LOG: [SLP] Adjust debug output for store vectorization failure

When store vectorization is infeasible, it's helpful to have a debug logging indication of why.  A case I've hit a couple times now is accidentally using -march instead of -mtriple and getting the default TTI results.  This causes max-vf to become 1, and thus hits the added logging line.

Added: 
    

Modified: 
    llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp

Removed: 
    


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diff  --git a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
index 126a9c4f9a3b..faec5611979d 100644
--- a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+++ b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
@@ -10408,6 +10408,11 @@ bool SLPVectorizerPass::vectorizeStores(ArrayRef<StoreInst *> Stores,
     unsigned MinVF = TTI->getStoreMinimumVF(
         R.getMinVF(DL->getTypeSizeInBits(ValueTy)), StoreTy, ValueTy);
 
+    if (MaxVF <= MinVF) {
+      LLVM_DEBUG(dbgs() << "SLP: Vectorization infeasible as MaxVF (" << MaxVF << ") <= "
+                        << "MinVF (" << MinVF << ")\n");
+    }
+
     // FIXME: Is division-by-2 the correct step? Should we assert that the
     // register size is a power-of-2?
     unsigned StartIdx = 0;