[llvm] cdc012f - [PhaseOrdering] add test for issue #50778; NFC
Sanjay Patel via llvm-commits
llvm-commits at lists.llvm.org
Fri Sep 23 09:03:45 PDT 2022
Author: Sanjay Patel
Date: 2022-09-23T12:03:03-04:00
New Revision: cdc012fa2696434689c872abc4797a1ee8284ddf
URL: https://github.com/llvm/llvm-project/commit/cdc012fa2696434689c872abc4797a1ee8284ddf
DIFF: https://github.com/llvm/llvm-project/commit/cdc012fa2696434689c872abc4797a1ee8284ddf.diff
LOG: [PhaseOrdering] add test for issue #50778; NFC
Several different passes are involved to get the expected IR,
and we don't want that to break again.
Added:
llvm/test/Transforms/PhaseOrdering/X86/vec-shift.ll
Modified:
Removed:
compiler-rt/test/orc/TestCases/Darwin/x86-64/Inputs/dlopen-dlclose-x2.S
################################################################################
diff --git a/compiler-rt/test/orc/TestCases/Darwin/x86-64/Inputs/dlopen-dlclose-x2.S b/compiler-rt/test/orc/TestCases/Darwin/x86-64/Inputs/dlopen-dlclose-x2.S
deleted file mode 100644
index 3fbd1778878d..000000000000
--- a/compiler-rt/test/orc/TestCases/Darwin/x86-64/Inputs/dlopen-dlclose-x2.S
+++ /dev/null
@@ -1,90 +0,0 @@
-// Runs a sequence of dlopen, dlclose, dlopen, dlclose on a library "inits".
-// This is intended as a standard harness for testing constructor / destructor
-// behavior in the context of a full dlclose and then re-dlopen'ing of the
-// inits library.
-//
-// Compiled from:
-//
-// int main(int argc, char *argv[]) {
-// printf("entering main\n");
-// void *H = dlopen("inits", 0);
-// if (!H) {
-// printf("failed\n");
-// return -1;
-// }
-// if (dlclose(H) == -1) {
-// printf("failed\n");
-// return -1;
-// }
-// H = dlopen("inits", 0);
-// if (!H) {
-// printf("failed\n");
-// return -1;
-// }
-// if (dlclose(H) == -1) {
-// printf("failed\n");
-// return -1;
-// }
-// printf("leaving main\n");
-// return 0;
-//}
-
- .section __TEXT,__text,regular,pure_instructions
- .build_version macos, 13, 0 sdk_version 13, 0
- .globl _main
- .p2align 4, 0x90
-_main:
-
- pushq %r14
- pushq %rbx
- pushq %rax
- leaq L_str(%rip), %rdi
- callq _puts
- leaq L_.str.1(%rip), %rdi
- xorl %esi, %esi
- callq _dlopen
- movl $-1, %ebx
- leaq L_str.8(%rip), %r14
- testq %rax, %rax
- je LBB0_4
-
- movq %rax, %rdi
- callq _dlclose
- cmpl $-1, %eax
- je LBB0_4
-
- leaq L_.str.1(%rip), %rdi
- xorl %esi, %esi
- callq _dlopen
- testq %rax, %rax
- je LBB0_4
-
- movq %rax, %rdi
- callq _dlclose
- xorl %ebx, %ebx
- cmpl $-1, %eax
- sete %bl
- leaq L_str.8(%rip), %rax
- leaq L_str.6(%rip), %r14
- cmoveq %rax, %r14
- negl %ebx
-LBB0_4:
- movq %r14, %rdi
- callq _puts
- movl %ebx, %eax
- addq $8, %rsp
- popq %rbx
- popq %r14
- retq
-
- .section __TEXT,__cstring,cstring_literals
-L_.str.1:
- .asciz "inits"
-L_str:
- .asciz "entering main"
-L_str.6:
- .asciz "leaving main"
-L_str.8:
- .asciz "failed"
-
-.subsections_via_symbols
diff --git a/llvm/test/Transforms/PhaseOrdering/X86/vec-shift.ll b/llvm/test/Transforms/PhaseOrdering/X86/vec-shift.ll
new file mode 100644
index 000000000000..34f870d89841
--- /dev/null
+++ b/llvm/test/Transforms/PhaseOrdering/X86/vec-shift.ll
@@ -0,0 +1,95 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt -passes="default<O3>" -S < %s | FileCheck %s --check-prefix=SSE
+; RUN: opt -passes="default<O3>" -S -mattr=avx < %s | FileCheck %s --check-prefix=AVX
+
+; This test is based on https://github.com/llvm/llvm-project/issues/50778
+; It's the unoptimized IR passed through -mem2reg to remove obvious noise.
+; This should show cooperation between instcombine, unrolling, inlining,
+; and SLP to create the target-optimal vector math+logic ops.
+
+target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-unknown-linux-gnu"
+
+define noundef i64 @foo(i64 noundef %0) {
+; CHECK-LABEL: @foo(
+; CHECK-NEXT: [[TMP2:%.*]] = shl i64 [[TMP0:%.*]], 44
+; CHECK-NEXT: [[TMP3:%.*]] = sub nuw nsw i64 -17592186044416, [[TMP2]]
+; CHECK-NEXT: ret i64 [[TMP3]]
+;
+; SSE-LABEL: @foo(
+; SSE-NEXT: [[TMP2:%.*]] = shl i64 [[TMP0:%.*]], 44
+; SSE-NEXT: [[TMP3:%.*]] = sub nuw nsw i64 -17592186044416, [[TMP2]]
+; SSE-NEXT: ret i64 [[TMP3]]
+;
+; AVX-LABEL: @foo(
+; AVX-NEXT: [[TMP2:%.*]] = shl i64 [[TMP0:%.*]], 44
+; AVX-NEXT: [[TMP3:%.*]] = sub nuw nsw i64 -17592186044416, [[TMP2]]
+; AVX-NEXT: ret i64 [[TMP3]]
+;
+ %2 = sub i64 1048575, %0
+ %3 = shl i64 %2, 44
+ ret i64 %3
+}
+
+define void @bar(ptr noundef %0) {
+; SSE-LABEL: @bar(
+; SSE-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr [[TMP0:%.*]], align 8
+; SSE-NEXT: [[TMP3:%.*]] = shl <2 x i64> [[TMP2]], <i64 44, i64 44>
+; SSE-NEXT: [[TMP4:%.*]] = sub nuw nsw <2 x i64> <i64 -17592186044416, i64 -17592186044416>, [[TMP3]]
+; SSE-NEXT: store <2 x i64> [[TMP4]], ptr [[TMP0]], align 8
+; SSE-NEXT: [[TMP5:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i64 2
+; SSE-NEXT: [[TMP6:%.*]] = load <2 x i64>, ptr [[TMP5]], align 8
+; SSE-NEXT: [[TMP7:%.*]] = shl <2 x i64> [[TMP6]], <i64 44, i64 44>
+; SSE-NEXT: [[TMP8:%.*]] = sub nuw nsw <2 x i64> <i64 -17592186044416, i64 -17592186044416>, [[TMP7]]
+; SSE-NEXT: store <2 x i64> [[TMP8]], ptr [[TMP5]], align 8
+; SSE-NEXT: [[TMP9:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i64 4
+; SSE-NEXT: [[TMP10:%.*]] = load <2 x i64>, ptr [[TMP9]], align 8
+; SSE-NEXT: [[TMP11:%.*]] = shl <2 x i64> [[TMP10]], <i64 44, i64 44>
+; SSE-NEXT: [[TMP12:%.*]] = sub nuw nsw <2 x i64> <i64 -17592186044416, i64 -17592186044416>, [[TMP11]]
+; SSE-NEXT: store <2 x i64> [[TMP12]], ptr [[TMP9]], align 8
+; SSE-NEXT: [[TMP13:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i64 6
+; SSE-NEXT: [[TMP14:%.*]] = load <2 x i64>, ptr [[TMP13]], align 8
+; SSE-NEXT: [[TMP15:%.*]] = shl <2 x i64> [[TMP14]], <i64 44, i64 44>
+; SSE-NEXT: [[TMP16:%.*]] = sub nuw nsw <2 x i64> <i64 -17592186044416, i64 -17592186044416>, [[TMP15]]
+; SSE-NEXT: store <2 x i64> [[TMP16]], ptr [[TMP13]], align 8
+; SSE-NEXT: ret void
+;
+; AVX-LABEL: @bar(
+; AVX-NEXT: [[TMP2:%.*]] = load <4 x i64>, ptr [[TMP0:%.*]], align 8
+; AVX-NEXT: [[TMP3:%.*]] = shl <4 x i64> [[TMP2]], <i64 44, i64 44, i64 44, i64 44>
+; AVX-NEXT: [[TMP4:%.*]] = sub nuw nsw <4 x i64> <i64 -17592186044416, i64 -17592186044416, i64 -17592186044416, i64 -17592186044416>, [[TMP3]]
+; AVX-NEXT: store <4 x i64> [[TMP4]], ptr [[TMP0]], align 8
+; AVX-NEXT: [[TMP5:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i64 4
+; AVX-NEXT: [[TMP6:%.*]] = load <4 x i64>, ptr [[TMP5]], align 8
+; AVX-NEXT: [[TMP7:%.*]] = shl <4 x i64> [[TMP6]], <i64 44, i64 44, i64 44, i64 44>
+; AVX-NEXT: [[TMP8:%.*]] = sub nuw nsw <4 x i64> <i64 -17592186044416, i64 -17592186044416, i64 -17592186044416, i64 -17592186044416>, [[TMP7]]
+; AVX-NEXT: store <4 x i64> [[TMP8]], ptr [[TMP5]], align 8
+; AVX-NEXT: ret void
+;
+ br label %2
+
+2: ; preds = %12, %1
+ %.0 = phi i32 [ 0, %1 ], [ %13, %12 ]
+ %3 = icmp slt i32 %.0, 8
+ br i1 %3, label %5, label %4
+
+4: ; preds = %2
+ br label %14
+
+5: ; preds = %2
+ %6 = sext i32 %.0 to i64
+ %7 = getelementptr inbounds i64, ptr %0, i64 %6
+ %8 = load i64, ptr %7, align 8
+ %9 = call noundef i64 @foo(i64 noundef %8)
+ %10 = sext i32 %.0 to i64
+ %11 = getelementptr inbounds i64, ptr %0, i64 %10
+ store i64 %9, ptr %11, align 8
+ br label %12
+
+12: ; preds = %5
+ %13 = add nsw i32 %.0, 1
+ br label %2
+
+14: ; preds = %4
+ ret void
+}
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