[PATCH] D130692: [AArch64][SVE] Expand gather index to 32 bits instead of 64 bits

[Paul Walker via Phabricator via llvm-commits]

paulwalker-arm added inline comments.


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:17873
+  if (ISD::isVectorShrinkable(Index.getNode(), 32, N->isIndexSigned()) &&
+      !(DataVT.getScalarSizeInBits() == 64 && DataVT.isFixedLengthVector())) {
     EVT NewIndexVT = IndexVT.changeVectorElementType(MVT::i32);
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Please pull this out into a separate check before this block, along with a suitable comment.  The "fix" is not really related to `isVectorShrinkable`, it is just that today that is the only logic applicable for fixed length vectors. However, this might change in the future hence why I prefer an isolated check.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D130692/new/

https://reviews.llvm.org/D130692