[PATCH] D134365: [LoongArch] Add support for llvm.trap and llvm.debugtrap

Fri Sep 23 03:12:27 PDT 2022

xry111 added a comment.

In D134365#3811041 <https://reviews.llvm.org/D134365#3811041>, @SixWeining wrote:

> In D134365#3806160 <https://reviews.llvm.org/D134365#3806160>, @xry111 wrote:
>
>> In D134365#3806143 <https://reviews.llvm.org/D134365#3806143>, @xry111 wrote:
>>
>>> I have some doubt here: on x86_64 a `trap` leads to SIGILL, but a `debugtrap` leads to SIGTRAP.  Not sure if they have a good reason or this is just for satisfying some "habit" of x86 programmers.
>>>
>>> If we want a SIGILL we can `amswap.w $r0, $r0, $r0`.
>>
>> I used `amswap.w $r0, $r0, $r1` in my early work <https://github.com/xry111/llvm-project/blob/1f1a3723c2614033e97e28ccee8438f1421bb4da/llvm/lib/Target/LoongArch/LoongArchInstrInfo.td#L1358>.  But again I'm not sure if we want a SIGTRAP of SIGILL (or something else) here.
>
> Do you mean when `rd == rj` (but not `rd == rk`)?

It's the only way mentioned by the ISA manual to reliably trigger an INE.  IIRC on a 3A5000LL `amswap.w $r0, $r0, $r0` also works but the manual is some sort of cryptic about the behavior when `rd == rj` and `rd == rk`, so I avoided `rd == rk`.

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