[PATCH] D134266: Introduce predicate for a atomic operations in GMIR

[Yashwant Singh via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG3fe71809a5d6: Introduce predicate for a atomic operations in GMIR (authored by yassingh).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D134266/new/

https://reviews.llvm.org/D134266

Files:
  llvm/include/llvm/CodeGen/TargetInstrInfo.h
  llvm/include/llvm/Support/TargetOpcodes.def


Index: llvm/include/llvm/Support/TargetOpcodes.def
===================================================================
--- llvm/include/llvm/Support/TargetOpcodes.def
+++ llvm/include/llvm/Support/TargetOpcodes.def
@@ -387,6 +387,12 @@
 HANDLE_TARGET_OPCODE(G_ATOMICRMW_FMAX)
 HANDLE_TARGET_OPCODE(G_ATOMICRMW_FMIN)
 
+// Marker for start of Generic AtomicRMW opcodes
+HANDLE_TARGET_OPCODE_MARKER(GENERIC_ATOMICRMW_OP_START, G_ATOMICRMW_XCHG)
+
+// Marker for end of Generic AtomicRMW opcodes
+HANDLE_TARGET_OPCODE_MARKER(GENERIC_ATOMICRMW_OP_END, G_ATOMICRMW_FMIN)
+
 // Generic atomic fence
 HANDLE_TARGET_OPCODE(G_FENCE)
 
Index: llvm/include/llvm/CodeGen/TargetInstrInfo.h
===================================================================
--- llvm/include/llvm/CodeGen/TargetInstrInfo.h
+++ llvm/include/llvm/CodeGen/TargetInstrInfo.h
@@ -110,6 +110,11 @@
     return Opc <= TargetOpcode::GENERIC_OP_END;
   }
 
+  static bool isGenericAtomicRMWOpcode(unsigned Opc) {
+    return Opc >= TargetOpcode::GENERIC_ATOMICRMW_OP_START &&
+           Opc <= TargetOpcode::GENERIC_ATOMICRMW_OP_END;
+  }
+
   /// Given a machine instruction descriptor, returns the register
   /// class constraint for OpNum, or NULL.
   virtual


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