[llvm] 779ccae - [RISCV] Precommit test showing scatter addressing gap

[Philip Reames via llvm-commits]

Author: Philip Reames
Date: 2022-09-22T12:21:47-07:00
New Revision: 779ccaea4f1fee447bd9b20c59f2aafb5c072ebe

URL: https://github.com/llvm/llvm-project/commit/779ccaea4f1fee447bd9b20c59f2aafb5c072ebe
DIFF: https://github.com/llvm/llvm-project/commit/779ccaea4f1fee447bd9b20c59f2aafb5c072ebe.diff

LOG: [RISCV] Precommit test showing scatter addressing gap

Added: 
    llvm/test/CodeGen/RISCV/rvv/mscatter-combine.ll

Modified: 
    

Removed: 
    


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diff  --git a/llvm/test/CodeGen/RISCV/rvv/mscatter-combine.ll b/llvm/test/CodeGen/RISCV/rvv/mscatter-combine.ll
new file mode 100644
index 000000000000..9c90f8acaed8
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/mscatter-combine.ll
@@ -0,0 +1,40 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+m,+d,+zfh,+experimental-zvfh,+v -target-abi=ilp32d \
+; RUN:     -verify-machineinstrs < %s | FileCheck %s --check-prefixes=RV32
+; RUN: llc -mtriple=riscv64 -mattr=+m,+d,+zfh,+experimental-zvfh,+v -target-abi=lp64d \
+; RUN:     -verify-machineinstrs < %s | FileCheck %s --check-prefixes=RV64
+
+%struct = type { i64, i64, ptr, i32, i32, i32, [4 x i32] }
+
+define void @complex_gep(ptr %p, <vscale x 2 x i64> %vec.ind, <vscale x 2 x i1> %m) {
+; RV32-LABEL: complex_gep:
+; RV32:       # %bb.0:
+; RV32-NEXT:    vsetvli a1, zero, e32, m1, ta, mu
+; RV32-NEXT:    vmv.v.x v10, a0
+; RV32-NEXT:    vnsrl.wi v11, v8, 0
+; RV32-NEXT:    li a0, 48
+; RV32-NEXT:    vmadd.vx v11, a0, v10
+; RV32-NEXT:    li a0, 28
+; RV32-NEXT:    vadd.vx v8, v11, a0
+; RV32-NEXT:    vmv.v.i v9, 0
+; RV32-NEXT:    vsoxei32.v v9, (zero), v8, v0.t
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: complex_gep:
+; RV64:       # %bb.0:
+; RV64-NEXT:    vsetvli a1, zero, e64, m2, ta, mu
+; RV64-NEXT:    vmv.v.x v10, a0
+; RV64-NEXT:    li a0, 56
+; RV64-NEXT:    vmacc.vx v10, a0, v8
+; RV64-NEXT:    li a0, 32
+; RV64-NEXT:    vadd.vx v8, v10, a0
+; RV64-NEXT:    vsetvli zero, zero, e32, m1, ta, mu
+; RV64-NEXT:    vmv.v.i v10, 0
+; RV64-NEXT:    vsoxei64.v v10, (zero), v8, v0.t
+; RV64-NEXT:    ret
+  %gep = getelementptr inbounds %struct, ptr %p, <vscale x 2 x i64> %vec.ind, i32 5
+  call void @llvm.masked.scatter.nxv2i32.nxv2p0(<vscale x 2 x i32> zeroinitializer, <vscale x 2 x ptr> %gep, i32 8, <vscale x 2 x i1> %m)
+  ret void
+}
+
+declare void @llvm.masked.scatter.nxv2i32.nxv2p0(<vscale x 2 x i32>, <vscale x 2 x ptr>, i32, <vscale x 2 x i1>)