[PATCH] D133850: [AArch64] Improve codegen for "trunc <4 x i64> to <4 x i8>" for all cases

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0x59616e added a comment.

I have a  question : how does the SIMD instruction view the vector register ?

This question is raised from the confusing execution result of qemu-aarch64_be with the following instructions

  fmov d0, x0
  mov v0.d[1], x1

Suppose the content of $x0 and $x1 is `0x102030405060708` and  `0x90a0b0c0e0f00` respectively. Here is the content of the $v0 after the above instructions is executed:

  (gdb) p $v0.b
  $14 = {u = {9, 10, 11, 12, 13, 14, 15, 0, 1, 2, 3, 4, 5, 6, 7, 8}...

This confuses me. In my understanding, it should be:

  {u = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 0}...

What goes wrong here ? Does the SIMD instruction view the last element of the vector register as the 0th one in big endian mode ? Where can I find information related to this ?

Thanks  :)


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https://reviews.llvm.org/D133850