[PATCH] D133810: [RISCV] Verify consistency of a couple TSFlags related to vector operands
Philip Reames via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu Sep 22 08:35:47 PDT 2022
This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGe41765aa4dc0: [RISCV] Verify consistency of a couple TSFlags related to vector operands (authored by reames).
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D133810/new/
https://reviews.llvm.org/D133810
Files:
llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
Index: llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
===================================================================
--- llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -1237,6 +1237,10 @@
return false;
}
}
+ if (!RISCVII::hasSEWOp(TSFlags)) {
+ ErrInfo = "VL operand w/o SEW operand?";
+ return false;
+ }
}
if (RISCVII::hasSEWOp(TSFlags)) {
unsigned OpIdx = RISCVII::getSEWOpNum(Desc);
@@ -1258,6 +1262,10 @@
ErrInfo = "Invalid Policy Value";
return false;
}
+ if (!RISCVII::hasVLOp(TSFlags)) {
+ ErrInfo = "policy operand w/o VL operand?";
+ return false;
+ }
}
return true;
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