[llvm] e41765a - [RISCV] Verify consistency of a couple TSFlags related to vector operands

[Philip Reames via llvm-commits]

Author: Philip Reames
Date: 2022-09-22T08:35:17-07:00
New Revision: e41765aa4dc034ca582d2d1df7944c1c1b3a9ba7

URL: https://github.com/llvm/llvm-project/commit/e41765aa4dc034ca582d2d1df7944c1c1b3a9ba7
DIFF: https://github.com/llvm/llvm-project/commit/e41765aa4dc034ca582d2d1df7944c1c1b3a9ba7.diff

LOG: [RISCV] Verify consistency of a couple TSFlags related to vector operands

Various bits of existing code assume the presence of one operand implies the presence of another.  Add verifier rules to catch violations.

Differential Revision: https://reviews.llvm.org/D133810

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index 1afd2fb40f54..98ae36012200 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -1237,6 +1237,10 @@ bool RISCVInstrInfo::verifyInstruction(const MachineInstr &MI,
         return false;
       }
     }
+    if (!RISCVII::hasSEWOp(TSFlags)) {
+      ErrInfo = "VL operand w/o SEW operand?";
+      return false;
+    }
   }
   if (RISCVII::hasSEWOp(TSFlags)) {
     unsigned OpIdx = RISCVII::getSEWOpNum(Desc);
@@ -1258,6 +1262,10 @@ bool RISCVInstrInfo::verifyInstruction(const MachineInstr &MI,
       ErrInfo = "Invalid Policy Value";
       return false;
     }
+    if (!RISCVII::hasVLOp(TSFlags)) {
+      ErrInfo = "policy operand w/o VL operand?";
+      return false;
+    }
   }
 
   return true;