[llvm] d6cb8f8 - [RISCV] Formatting fixes to RISCV.td NFC
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Thu Sep 22 08:13:41 PDT 2022
Author: Craig Topper
Date: 2022-09-22T08:12:59-07:00
New Revision: d6cb8f85bf98a2634222e758d31011c18b8d0624
URL: https://github.com/llvm/llvm-project/commit/d6cb8f85bf98a2634222e758d31011c18b8d0624
DIFF: https://github.com/llvm/llvm-project/commit/d6cb8f85bf98a2634222e758d31011c18b8d0624.diff
LOG: [RISCV] Formatting fixes to RISCV.td NFC
Improve indentation. Fix the worst of the 80 column violations.
Added:
Modified:
llvm/lib/Target/RISCV/RISCV.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCV.td b/llvm/lib/Target/RISCV/RISCV.td
index 84ff6883d0d1..593ecfa879dd 100644
--- a/llvm/lib/Target/RISCV/RISCV.td
+++ b/llvm/lib/Target/RISCV/RISCV.td
@@ -208,34 +208,38 @@ def HasStdExtZbbOrZbkb
"'Zbb' (Basic Bit-Manipulation) or "
"'Zbkb' (Bitmanip instructions for Cryptography)">;
-// The Carry-less multiply subextension for cryptography is a subset of basic carry-less multiply subextension. The former should be enabled if the latter is enabled.
+// The Carry-less multiply subextension for cryptography is a subset of basic
+// carry-less multiply subextension. The former should be enabled if the latter
+// is enabled.
def FeatureStdExtZbkc
: SubtargetFeature<"zbkc", "HasStdExtZbkc", "true",
- "'Zbkc' (Carry-less multiply instructions for Cryptography)">;
+ "'Zbkc' (Carry-less multiply instructions for "
+ "Cryptography)">;
def HasStdExtZbkc
: Predicate<"Subtarget->hasStdExtZbkc()">,
- AssemblerPredicate<(all_of FeatureStdExtZbkc),
- "'Zbkc' (Carry-less multiply instructions for Cryptography)">;
+ AssemblerPredicate<(all_of FeatureStdExtZbkc),
+ "'Zbkc' (Carry-less multiply instructions for Cryptography)">;
def HasStdExtZbcOrZbkc
: Predicate<"Subtarget->hasStdExtZbc() || Subtarget->hasStdExtZbkc()">,
AssemblerPredicate<(any_of FeatureStdExtZbc, FeatureStdExtZbkc),
"'Zbc' (Carry-Less Multiplication) or "
- "'Zbkc' (Carry-less multiply instructions for Cryptography)">;
+ "'Zbkc' (Carry-less multiply instructions "
+ "for Cryptography)">;
def FeatureStdExtZknd
: SubtargetFeature<"zknd", "HasStdExtZknd", "true",
"'Zknd' (NIST Suite: AES Decryption)">;
def HasStdExtZknd : Predicate<"Subtarget->hasStdExtZknd()">,
- AssemblerPredicate<(all_of FeatureStdExtZknd),
- "'Zknd' (NIST Suite: AES Decryption)">;
+ AssemblerPredicate<(all_of FeatureStdExtZknd),
+ "'Zknd' (NIST Suite: AES Decryption)">;
def FeatureStdExtZkne
: SubtargetFeature<"zkne", "HasStdExtZkne", "true",
"'Zkne' (NIST Suite: AES Encryption)">;
def HasStdExtZkne : Predicate<"Subtarget->hasStdExtZkne()">,
- AssemblerPredicate<(all_of FeatureStdExtZkne),
- "'Zkne' (NIST Suite: AES Encryption)">;
+ AssemblerPredicate<(all_of FeatureStdExtZkne),
+ "'Zkne' (NIST Suite: AES Encryption)">;
// Some instructions belong to both Zknd and Zkne subextensions.
// They should be enabled if either has been specified.
@@ -263,8 +267,9 @@ def FeatureStdExtZksh
: SubtargetFeature<"zksh", "HasStdExtZksh", "true",
"'Zksh' (ShangMi Suite: SM3 Hash Function Instructions)">;
def HasStdExtZksh : Predicate<"Subtarget->hasStdExtZksh()">,
- AssemblerPredicate<(all_of FeatureStdExtZksh),
- "'Zksh' (ShangMi Suite: SM3 Hash Function Instructions)">;
+ AssemblerPredicate<(all_of FeatureStdExtZksh),
+ "'Zksh' (ShangMi Suite: SM3 Hash Function "
+ "Instructions)">;
def FeatureStdExtZkr
: SubtargetFeature<"zkr", "HasStdExtZkr", "true",
@@ -305,13 +310,15 @@ def FeatureStdExtZk
def FeatureExtZca
: SubtargetFeature<"experimental-zca", "HasStdExtZca", "true",
- "'Zca' (part of the C extension, excluding compressed floating point loads/stores)">;
+ "'Zca' (part of the C extension, excluding compressed "
+ "floating point loads/stores)">;
def HasStdExtCOrZca
: Predicate<"Subtarget->hasStdExtC() || Subtarget->hasStdExtZca()">,
AssemblerPredicate<(any_of FeatureStdExtC, FeatureExtZca),
"'C' (Compressed Instructions) or "
- "'Zca' (part of the C extension, excluding compressed floating point loads/stores)">;
+ "'Zca' (part of the C extension, excluding "
+ "compressed floating point loads/stores)">;
def FeatureNoRVCHints
: SubtargetFeature<"no-rvc-hints", "EnableRVCHintInstrs", "false",
@@ -321,14 +328,14 @@ def HasRVCHints : Predicate<"Subtarget->enableRVCHintInstrs()">,
"RVC Hint Instructions">;
def FeatureStdExtZvl32b : SubtargetFeature<"zvl32b", "ZvlLen", "32",
- "'Zvl' (Minimum Vector Length) 32">;
+ "'Zvl' (Minimum Vector Length) 32">;
foreach i = { 6-15 } in {
- defvar I = !shl(1, i);
- def FeatureStdExtZvl#I#b :
- SubtargetFeature<"zvl"#I#"b", "ZvlLen", !cast<string>(I),
- "'Zvl' (Minimum Vector Length) "#I,
- [!cast<SubtargetFeature>("FeatureStdExtZvl"#!srl(I, 1)#"b")]>;
+ defvar I = !shl(1, i);
+ def FeatureStdExtZvl#I#b :
+ SubtargetFeature<"zvl"#I#"b", "ZvlLen", !cast<string>(I),
+ "'Zvl' (Minimum Vector Length) "#I,
+ [!cast<SubtargetFeature>("FeatureStdExtZvl"#!srl(I, 1)#"b")]>;
}
def FeatureStdExtZve32x
@@ -346,7 +353,8 @@ def FeatureStdExtZve32f
def FeatureStdExtZve64x
: SubtargetFeature<"zve64x", "HasStdExtZve64x", "true",
"'Zve64x' (Vector Extensions for Embedded Processors "
- "with maximal 64 EEW)", [FeatureStdExtZve32x, FeatureStdExtZvl64b]>;
+ "with maximal 64 EEW)",
+ [FeatureStdExtZve32x, FeatureStdExtZvl64b]>;
def FeatureStdExtZve64f
: SubtargetFeature<"zve64f", "HasStdExtZve64f", "true",
@@ -363,7 +371,8 @@ def FeatureStdExtZve64d
def FeatureStdExtV
: SubtargetFeature<"v", "HasStdExtV", "true",
"'V' (Vector Extension for Application Processors)",
- [FeatureStdExtZvl128b, FeatureStdExtZve64d, FeatureStdExtF, FeatureStdExtD]>;
+ [FeatureStdExtZvl128b, FeatureStdExtZve64d,
+ FeatureStdExtF, FeatureStdExtD]>;
def HasVInstructions : Predicate<"Subtarget->hasVInstructions()">,
AssemblerPredicate<
@@ -411,15 +420,15 @@ def FeatureStdExtZtso
: SubtargetFeature<"experimental-ztso", "HasStdExtZtso", "true",
"'Ztso' (Memory Model - Total Store Order)">;
def HasStdExtZtso : Predicate<"Subtarget->hasStdExtZTso()">,
- AssemblerPredicate<(all_of FeatureStdExtZtso),
- "'Ztso' (Memory Model - Total Store Order)">;
+ AssemblerPredicate<(all_of FeatureStdExtZtso),
+ "'Ztso' (Memory Model - Total Store Order)">;
def FeatureStdExtZawrs
: SubtargetFeature<"experimental-zawrs", "HasStdExtZawrs", "true",
"'Zawrs' (Wait on Reservation Set)">;
def HasStdExtZawrs : Predicate<"Subtarget->hasStdExtZawrs()">,
- AssemblerPredicate<(all_of FeatureStdExtZawrs),
- "'Zawrs' (Wait on Reservation Set)">;
+ AssemblerPredicate<(all_of FeatureStdExtZawrs),
+ "'Zawrs' (Wait on Reservation Set)">;
// Feature32Bit exists to mark CPUs that support RV32 to distinquish them from
// tuning CPU names.
@@ -429,10 +438,10 @@ def Feature64Bit
: SubtargetFeature<"64bit", "HasRV64", "true", "Implements RV64">;
def IsRV64 : Predicate<"Subtarget->is64Bit()">,
AssemblerPredicate<(all_of Feature64Bit),
- "RV64I Base Instruction Set">;
+ "RV64I Base Instruction Set">;
def IsRV32 : Predicate<"!Subtarget->is64Bit()">,
AssemblerPredicate<(all_of (not Feature64Bit)),
- "RV32I Base Instruction Set">;
+ "RV32I Base Instruction Set">;
defvar RV32 = DefaultMode;
def RV64 : HwMode<"+64bit">;
@@ -448,9 +457,9 @@ def FeatureRelax
"Enable Linker relaxation.">;
foreach i = {1-31} in
- def FeatureReserveX#i :
- SubtargetFeature<"reserve-x"#i, "UserReservedRegister[RISCV::X"#i#"]",
- "true", "Reserve X"#i>;
+ def FeatureReserveX#i :
+ SubtargetFeature<"reserve-x"#i, "UserReservedRegister[RISCV::X"#i#"]",
+ "true", "Reserve X"#i>;
def FeatureSaveRestore : SubtargetFeature<"save-restore", "EnableSaveRestore",
"true", "Enable save/restore.">;
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