[PATCH] D134438: POC patch to demonstrate how new intrinsics for interleaved load/store could be used in LoopVectorize
mgabka via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu Sep 22 06:49:15 PDT 2022
mgabka created this revision.
mgabka added reviewers: paulwalker-arm, david-arm, fhahn, sdesmalen.
Herald added subscribers: shiva0217, nlopes, ctetreau, hiraditya.
Herald added a project: All.
mgabka requested review of this revision.
Herald added subscribers: llvm-commits, pcwang-thead, alextsao1999, jdoerfert.
Herald added a project: LLVM.
This patch needs to be broken down into smaller chunks.
The purpose of this patch is to demonstrate how new, generic LLVM intrinsics
could be emitted directly from inside LoopVectorize,
and later transformed into a target specific ones.
This POC patch focuses on the SVE side, however the intention is to not limit it
only to SVE. Code generation for NEON can also use this approach.
The motivation for such solution is that at the vectorization stage we already
know if we are handling interleaved memory accesses or not, so we can use
that knowledge to emit dedicated intrinsics for such accesses.
The current LLVM's implementation uses shufflevector to interleave
the data after/before load/store what is not suitable for scalable vectors.
https://reviews.llvm.org/D134438
Files:
llvm/include/llvm/Analysis/TargetTransformInfo.h
llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
llvm/include/llvm/CodeGen/TargetLowering.h
llvm/include/llvm/IR/IRBuilder.h
llvm/include/llvm/IR/Intrinsics.td
llvm/lib/Analysis/TargetTransformInfo.cpp
llvm/lib/CodeGen/InterleavedAccessPass.cpp
llvm/lib/IR/IRBuilder.cpp
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
llvm/lib/Target/AArch64/AArch64ISelLowering.h
llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h
llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
llvm/test/Transforms/InterleavedAccess/AArch64/sve-interleaved-accesses-load.ll
llvm/test/Transforms/InterleavedAccess/AArch64/sve-interleaved-accesses-store.ll
llvm/test/Transforms/LoopVectorize/AArch64/scalable-strict-fadd.ll
llvm/test/Transforms/LoopVectorize/AArch64/sve-tail-folding-option.ll
llvm/test/Transforms/LoopVectorize/AArch64/sve-widen-phi.ll
llvm/test/Transforms/LoopVectorize/sve-interleaved-accesses-ic-2.ll
llvm/test/Transforms/LoopVectorize/sve-interleaved-accesses.ll
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