[PATCH] D134412: [LoongArch] Support 'generic' as a valid CPU name

[WÁNG Xuěruì via Phabricator via llvm-commits]

xen0n updated this revision to Diff 462162.
xen0n added a comment.

add testcase


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D134412/new/

https://reviews.llvm.org/D134412

Files:
  llvm/lib/Target/LoongArch/LoongArch.td
  llvm/lib/Target/LoongArch/LoongArchSubtarget.cpp
  llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchMCTargetDesc.cpp
  llvm/test/CodeGen/LoongArch/cpu-name-generic.ll


Index: llvm/test/CodeGen/LoongArch/cpu-name-generic.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/LoongArch/cpu-name-generic.ll
@@ -0,0 +1,29 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mcpu=generic < %s \
+; RUN:   | FileCheck %s --check-prefix=LA32
+; RUN: llc --mtriple=loongarch32 --mcpu=generic-la32 < %s \
+; RUN:   | FileCheck %s --check-prefix=LA32
+; RUN: llc --mtriple=loongarch64 --mcpu=generic < %s \
+; RUN:   | FileCheck %s --check-prefix=LA64
+; RUN: llc --mtriple=loongarch64 --mcpu=generic-la64 < %s \
+; RUN:   | FileCheck %s --check-prefix=LA64
+
+;; The CPU name "generic" should map to the corresponding concrete names
+;; according to the target triple's bitness.
+define i64 @f(i64 signext %a, i64 signext %b) {
+; LA32-LABEL: f:
+; LA32:       # %bb.0:
+; LA32-NEXT:    add.w $a1, $a1, $a3
+; LA32-NEXT:    add.w $a2, $a0, $a2
+; LA32-NEXT:    sltu $a0, $a2, $a0
+; LA32-NEXT:    add.w $a1, $a1, $a0
+; LA32-NEXT:    move $a0, $a2
+; LA32-NEXT:    ret
+;
+; LA64-LABEL: f:
+; LA64:       # %bb.0:
+; LA64-NEXT:    add.d $a0, $a0, $a1
+; LA64-NEXT:    ret
+  %1 = add nsw i64 %a, %b
+  ret i64 %1
+}
Index: llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchMCTargetDesc.cpp
===================================================================
--- llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchMCTargetDesc.cpp
+++ llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchMCTargetDesc.cpp
@@ -54,7 +54,7 @@
 
 static MCSubtargetInfo *
 createLoongArchMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) {
-  if (CPU.empty())
+  if (CPU.empty() || CPU == "generic")
     CPU = TT.isArch64Bit() ? "la464" : "generic-la32";
   return createLoongArchMCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, FS);
 }
Index: llvm/lib/Target/LoongArch/LoongArchSubtarget.cpp
===================================================================
--- llvm/lib/Target/LoongArch/LoongArchSubtarget.cpp
+++ llvm/lib/Target/LoongArch/LoongArchSubtarget.cpp
@@ -27,7 +27,7 @@
     const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS,
     StringRef ABIName) {
   bool Is64Bit = TT.isArch64Bit();
-  if (CPU.empty())
+  if (CPU.empty() || CPU == "generic")
     CPU = Is64Bit ? "generic-la64" : "generic-la32";
 
   if (TuneCPU.empty())
Index: llvm/lib/Target/LoongArch/LoongArch.td
===================================================================
--- llvm/lib/Target/LoongArch/LoongArch.td
+++ llvm/lib/Target/LoongArch/LoongArch.td
@@ -100,6 +100,10 @@
 def : ProcessorModel<"generic-la32", NoSchedModel, []>;
 def : ProcessorModel<"generic-la64", NoSchedModel, [Feature64Bit]>;
 
+// Support generic for compatibility with other targets. The triple will be used
+// to change to the appropriate la32/la64 version.
+def : ProcessorModel<"generic", NoSchedModel, []>;
+
 def : ProcessorModel<"la464", NoSchedModel, [Feature64Bit,
                                              FeatureExtLASX,
                                              FeatureExtLVZ,


-------------- next part --------------
A non-text attachment was scrubbed...
Name: D134412.462162.patch
Type: text/x-patch
Size: 3099 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20220922/333c4212/attachment.bin>