[PATCH] D134277: [RISCV] Combine comparison and logic ops.

[Anton Afanasyev via Phabricator via llvm-commits]

anton-afanasyev added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:8404
+  // Codes of selection operation. The first index selects signed, unsigned or
+  // float the second index selects MIN/MAX.
+  static constexpr ISD::NodeType SelectionCodes[2][2] = {
----------------
please adjust comment: no float


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  https://reviews.llvm.org/D134277/new/

https://reviews.llvm.org/D134277