[PATCH] D134151: [AMDGPU][GFX11] Mitigate VALU mask write hazard

[Jay Foad via Phabricator via llvm-commits]

foad added inline comments.


================
Comment at: llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp:2732
+    switch (I.getOpcode()) {
+    case AMDGPU::V_ADDC_U32_e32:
+    case AMDGPU::V_CNDMASK_B16_e32:
----------------
rampitec wrote:
> critson wrote:
> > rampitec wrote:
> > > Isn't that less error prone to just check for an implicit vcc use? I assume it shall not be true unless it reads a mask.
> > I am not sure I understand?
> > These instructions always implicitly read VCC.
> I mean instead of listing instruction opcodes it can use a general check is there is an implicit $vcc operand. But OK, if you think this list is comprehensive.
The _e32 versions have an implicit $vcc, but the _e64 versions do not.

There is still a small problem that the list of instructions here is missing exotic forms like V_CNDMASK_B32_dpp.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D134151/new/

https://reviews.llvm.org/D134151