[PATCH] D134418: [AMDGPU] Improve ISel for v_bfi instructions.

[Jay Foad via Phabricator via llvm-commits]

foad requested changes to this revision.
foad added inline comments.
This revision now requires changes to proceed.


================
Comment at: llvm/lib/Target/AMDGPU/SIInstructions.td:1908-1909
+// This handles nested bitfieldInserts:
+// ((a ^ y) & C0) ^ ((y & C1) | z & ~C1))) <=>
+// ((a & C0) | (~C0 | ((y & C1) | z & ~C1)))
+def : AMDGPUPat <
----------------
As written this is not true. Counterexample: a=x=y=C0=C1=0.


================
Comment at: llvm/lib/Target/AMDGPU/SIInstructions.td:1911
+def : AMDGPUPat <
+   (xor (and (xor i32:$a, i32:$y), (i32 imm:$imm0)),
+     (BFIImm32 i32:$x, i32:$y, i32:$z)),
----------------
Should have a `DivergentBinFrag` on the outermost node so that we don't select VALU instructions for uniform expressions.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D134418/new/

https://reviews.llvm.org/D134418