[llvm] 8b8e18e - [RISCV] Replace RISCVISD::GREV/GORC/SHFL/UNSHFL with BREV8/ORC_B/ZIP/UNZIP.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Wed Sep 21 22:00:26 PDT 2022
Author: Craig Topper
Date: 2022-09-21T21:57:59-07:00
New Revision: 8b8e18e11fa6f57f8a7c6f1ad2df9adfb7b6a019
URL: https://github.com/llvm/llvm-project/commit/8b8e18e11fa6f57f8a7c6f1ad2df9adfb7b6a019
DIFF: https://github.com/llvm/llvm-project/commit/8b8e18e11fa6f57f8a7c6f1ad2df9adfb7b6a019.diff
LOG: [RISCV] Replace RISCVISD::GREV/GORC/SHFL/UNSHFL with BREV8/ORC_B/ZIP/UNZIP.
With Zbp removed, we no longer need the generalized forms.
The computeKnownBitsForTargetNode code brev8/orc.b is still based
on the general form with the shift amount forced to 7.
Added:
Modified:
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
llvm/lib/Target/RISCV/RISCVISelLowering.h
llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
index f63367bf9353..2a6bdb2fb752 100644
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -2246,8 +2246,6 @@ bool RISCVDAGToDAGISel::hasAllNBitUsers(SDNode *Node, unsigned Bits) const {
Node->getOpcode() == ISD::MUL || Node->getOpcode() == ISD::SHL ||
Node->getOpcode() == ISD::SRL || Node->getOpcode() == ISD::AND ||
Node->getOpcode() == ISD::SIGN_EXTEND_INREG ||
- Node->getOpcode() == RISCVISD::GREV ||
- Node->getOpcode() == RISCVISD::GORC ||
isa<ConstantSDNode>(Node)) &&
"Unexpected opcode");
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 8c910b8d1e5e..5c1a8e76b5ee 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -3357,11 +3357,7 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
assert(Op.getOpcode() == ISD::BITREVERSE && "Unexpected opcode");
// Expand bitreverse to a bswap(rev8) followed by brev8.
SDValue BSwap = DAG.getNode(ISD::BSWAP, DL, VT, Op.getOperand(0));
- // We use the old Zbp grevi encoding for rev.b/brev8 which will be
- // recognized as brev8 by an isel pattern.
- // TODO: Replace with RISCVISD::BREV8.
- return DAG.getNode(RISCVISD::GREV, DL, VT, BSwap,
- DAG.getConstant(7, DL, VT));
+ return DAG.getNode(RISCVISD::BREV8, DL, VT, BSwap);
}
case ISD::TRUNCATE:
// Only custom-lower vector truncates
@@ -5052,22 +5048,15 @@ SDValue RISCVTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
}
case Intrinsic::riscv_orc_b:
case Intrinsic::riscv_brev8: {
- // Lower to the GORCI encoding for orc.b or the GREVI encoding for brev8.
unsigned Opc =
- IntNo == Intrinsic::riscv_brev8 ? RISCVISD::GREV : RISCVISD::GORC;
- return DAG.getNode(Opc, DL, XLenVT, Op.getOperand(1),
- DAG.getConstant(7, DL, XLenVT));
+ IntNo == Intrinsic::riscv_brev8 ? RISCVISD::BREV8 : RISCVISD::ORC_B;
+ return DAG.getNode(Opc, DL, XLenVT, Op.getOperand(1));
}
case Intrinsic::riscv_zip:
case Intrinsic::riscv_unzip: {
- // Lower to the SHFLI encoding for zip or the UNSHFLI encoding for unzip.
- // For i32 the immediate is 15. For i64 the immediate is 31.
unsigned Opc =
- IntNo == Intrinsic::riscv_zip ? RISCVISD::SHFL : RISCVISD::UNSHFL;
- unsigned BitWidth = Op.getValueSizeInBits();
- assert(isPowerOf2_32(BitWidth) && BitWidth >= 2 && "Unexpected bit width");
- return DAG.getNode(Opc, DL, XLenVT, Op.getOperand(1),
- DAG.getConstant((BitWidth / 2) - 1, DL, XLenVT));
+ IntNo == Intrinsic::riscv_zip ? RISCVISD::ZIP : RISCVISD::UNZIP;
+ return DAG.getNode(Opc, DL, XLenVT, Op.getOperand(1));
}
case Intrinsic::riscv_bcompress:
case Intrinsic::riscv_bdecompress: {
@@ -7431,18 +7420,14 @@ void RISCVTargetLowering::ReplaceNodeResults(SDNode *N,
}
break;
}
- case RISCVISD::GREV: {
+ case RISCVISD::BREV8: {
MVT VT = N->getSimpleValueType(0);
MVT XLenVT = Subtarget.getXLenVT();
assert((VT == MVT::i16 || (VT == MVT::i32 && Subtarget.is64Bit())) &&
"Unexpected custom legalisation");
- assert(isa<ConstantSDNode>(N->getOperand(1)) && "Expected constant");
- assert(Subtarget.hasStdExtZbkb() && N->getConstantOperandVal(1) == 7 &&
- "Unexpected extension");
- SDValue NewOp0 = DAG.getNode(ISD::ANY_EXTEND, DL, XLenVT, N->getOperand(0));
- SDValue NewOp1 =
- DAG.getNode(ISD::ZERO_EXTEND, DL, XLenVT, N->getOperand(1));
- SDValue NewRes = DAG.getNode(N->getOpcode(), DL, XLenVT, NewOp0, NewOp1);
+ assert(Subtarget.hasStdExtZbkb() && "Unexpected extension");
+ SDValue NewOp = DAG.getNode(ISD::ANY_EXTEND, DL, XLenVT, N->getOperand(0));
+ SDValue NewRes = DAG.getNode(N->getOpcode(), DL, XLenVT, NewOp);
// ReplaceNodeResults requires we maintain the same type for the return
// value.
Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, VT, NewRes));
@@ -7522,11 +7507,9 @@ void RISCVTargetLowering::ReplaceNodeResults(SDNode *N,
break;
}
case Intrinsic::riscv_orc_b: {
- // Lower to the GORCI encoding for orc.b with the operand extended.
SDValue NewOp =
DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, N->getOperand(1));
- SDValue Res = DAG.getNode(RISCVISD::GORC, DL, MVT::i64, NewOp,
- DAG.getConstant(7, DL, MVT::i64));
+ SDValue Res = DAG.getNode(RISCVISD::ORC_B, DL, MVT::i64, NewOp);
Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Res));
return;
}
@@ -7752,41 +7735,6 @@ static SDValue transformAddShlImm(SDNode *N, SelectionDAG &DAG,
return DAG.getNode(ISD::SHL, DL, VT, NA1, DAG.getConstant(Bits, DL, VT));
}
-// Combine (GREVI (GREVI x, C2), C1) -> (GREVI x, C1^C2) when C1^C2 is
-// non-zero, and to x when it is. Any repeated GREVI stage undoes itself.
-// Combine (GORCI (GORCI x, C2), C1) -> (GORCI x, C1|C2). Repeated stage does
-// not undo itself, but they are redundant.
-static SDValue combineGREVI_GORCI(SDNode *N, SelectionDAG &DAG) {
- bool IsGORC = N->getOpcode() == RISCVISD::GORC;
- assert((IsGORC || N->getOpcode() == RISCVISD::GREV) && "Unexpected opcode");
- SDValue Src = N->getOperand(0);
-
- if (Src.getOpcode() != N->getOpcode())
- return SDValue();
-
- if (!isa<ConstantSDNode>(N->getOperand(1)) ||
- !isa<ConstantSDNode>(Src.getOperand(1)))
- return SDValue();
-
- unsigned ShAmt1 = N->getConstantOperandVal(1);
- unsigned ShAmt2 = Src.getConstantOperandVal(1);
- Src = Src.getOperand(0);
-
- unsigned CombinedShAmt;
- if (IsGORC)
- CombinedShAmt = ShAmt1 | ShAmt2;
- else
- CombinedShAmt = ShAmt1 ^ ShAmt2;
-
- if (CombinedShAmt == 0)
- return Src;
-
- SDLoc DL(N);
- return DAG.getNode(
- N->getOpcode(), DL, N->getValueType(0), Src,
- DAG.getConstant(CombinedShAmt, DL, N->getOperand(1).getValueType()));
-}
-
// Combine a constant select operand into its use:
//
// (and (select cond, -1, c), x)
@@ -8551,8 +8499,7 @@ static SDValue performBITREVERSECombine(SDNode *N, SelectionDAG &DAG,
return SDValue();
SDLoc DL(N);
- return DAG.getNode(RISCVISD::GREV, DL, VT, Src.getOperand(0),
- DAG.getConstant(7, DL, VT));
+ return DAG.getNode(RISCVISD::BREV8, DL, VT, Src.getOperand(0));
}
// Convert from one FMA opcode to another based on whether we are negating the
@@ -8926,26 +8873,6 @@ SDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N,
return SDValue(N, 0);
break;
}
- case RISCVISD::GREV:
- case RISCVISD::GORC: {
- // Only the lower log2(Bitwidth) bits of the the shift amount are read.
- unsigned BitWidth = N->getOperand(1).getValueSizeInBits();
- assert(isPowerOf2_32(BitWidth) && "Unexpected bit width");
- if (SimplifyDemandedLowBitsHelper(1, Log2_32(BitWidth)))
- return SDValue(N, 0);
-
- return combineGREVI_GORCI(N, DAG);
- }
- case RISCVISD::SHFL:
- case RISCVISD::UNSHFL: {
- // Only the lower log2(Bitwidth)-1 bits of the the shift amount are read.
- unsigned BitWidth = N->getOperand(1).getValueSizeInBits();
- assert(isPowerOf2_32(BitWidth) && "Unexpected bit width");
- if (SimplifyDemandedLowBitsHelper(1, Log2_32(BitWidth) - 1))
- return SDValue(N, 0);
-
- break;
- }
case RISCVISD::BCOMPRESSW:
case RISCVISD::BDECOMPRESSW: {
// Only the lower 32 bits of LHS and RHS are read.
@@ -9576,17 +9503,16 @@ void RISCVTargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
Known.Zero.setBitsFrom(LowBits);
break;
}
- case RISCVISD::GREV:
- case RISCVISD::GORC: {
- if (auto *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
- Known = DAG.computeKnownBits(Op.getOperand(0), Depth + 1);
- unsigned ShAmt = C->getZExtValue() & (Known.getBitWidth() - 1);
- bool IsGORC = Op.getOpcode() == RISCVISD::GORC;
- // To compute zeros, we need to invert the value and invert it back after.
- Known.Zero =
- ~computeGREVOrGORC(~Known.Zero.getZExtValue(), ShAmt, IsGORC);
- Known.One = computeGREVOrGORC(Known.One.getZExtValue(), ShAmt, IsGORC);
- }
+ case RISCVISD::BREV8:
+ case RISCVISD::ORC_B: {
+ // FIXME: This is based on the non-ratified Zbp GREV and GORC where a
+ // control value of 7 is equivalent to brev8 and orc.b.
+ Known = DAG.computeKnownBits(Op.getOperand(0), Depth + 1);
+ bool IsGORC = Op.getOpcode() == RISCVISD::ORC_B;
+ // To compute zeros, we need to invert the value and invert it back after.
+ Known.Zero =
+ ~computeGREVOrGORC(~Known.Zero.getZExtValue(), 7, IsGORC);
+ Known.One = computeGREVOrGORC(Known.One.getZExtValue(), 7, IsGORC);
break;
}
case RISCVISD::READ_VLENB: {
@@ -9657,21 +9583,6 @@ unsigned RISCVTargetLowering::ComputeNumSignBitsForTargetNode(
// more precise answer could be calculated for SRAW depending on known
// bits in the shift amount.
return 33;
- case RISCVISD::SHFL:
- case RISCVISD::UNSHFL: {
- // There is no SHFLIW, but a i64 SHFLI with bit 4 of the control word
- // cleared doesn't affect bit 31. The upper 32 bits will be shuffled, but
- // will stay within the upper 32 bits. If there were more than 32 sign bits
- // before there will be at least 33 sign bits after.
- if (Op.getValueType() == MVT::i64 &&
- isa<ConstantSDNode>(Op.getOperand(1)) &&
- (Op.getConstantOperandVal(1) & 0x10) == 0) {
- unsigned Tmp = DAG.ComputeNumSignBits(Op.getOperand(0), Depth + 1);
- if (Tmp > 32)
- return 33;
- }
- break;
- }
case RISCVISD::VMV_X_S: {
// The number of sign bits of the scalar result is computed by obtaining the
// element type of the input vector operand, subtracting its width from the
@@ -11712,10 +11623,10 @@ const char *RISCVTargetLowering::getTargetNodeName(unsigned Opcode) const {
NODE_NAME_CASE(STRICT_FCVT_W_RV64)
NODE_NAME_CASE(STRICT_FCVT_WU_RV64)
NODE_NAME_CASE(READ_CYCLE_WIDE)
- NODE_NAME_CASE(GREV)
- NODE_NAME_CASE(GORC)
- NODE_NAME_CASE(SHFL)
- NODE_NAME_CASE(UNSHFL)
+ NODE_NAME_CASE(BREV8)
+ NODE_NAME_CASE(ORC_B)
+ NODE_NAME_CASE(ZIP)
+ NODE_NAME_CASE(UNZIP)
NODE_NAME_CASE(BFP)
NODE_NAME_CASE(BFPW)
NODE_NAME_CASE(BCOMPRESS)
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.h b/llvm/lib/Target/RISCV/RISCVISelLowering.h
index 14796d8bbc24..698aab609107 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.h
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.h
@@ -108,15 +108,12 @@ enum NodeType : unsigned {
// READ_CYCLE_WIDE - A read of the 64-bit cycle CSR on a 32-bit target
// (returns (Lo, Hi)). It takes a chain operand.
READ_CYCLE_WIDE,
- // Generalized Reverse and Generalized Or-Combine - directly matching the
- // semantics of the named RISC-V instructions. Lowered as custom nodes as
- // TableGen chokes when faced with commutative permutations in deeply-nested
- // DAGs. Each node takes an input operand and a control operand and outputs a
- // bit-manipulated version of input. All operands are i32 or XLenVT.
- GREV,
- GORC,
- SHFL,
- UNSHFL,
+ // brev8, orc.b, zip, and unzip from Zbb and Zbkb. All operands are i32 or
+ // XLenVT.
+ BREV8,
+ ORC_B,
+ ZIP,
+ UNZIP,
// Bit Compress/Decompress implement the generic bit extract and bit deposit
// functions. This operation is also referred to as bit gather/scatter, bit
// pack/unpack, parallel extract/deposit, compress/expand, or right
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
index 85811c94f839..8b17976b2738 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
@@ -37,14 +37,10 @@ def riscv_clzw : SDNode<"RISCVISD::CLZW", SDT_RISCVIntUnaryOpW>;
def riscv_ctzw : SDNode<"RISCVISD::CTZW", SDT_RISCVIntUnaryOpW>;
def riscv_rolw : SDNode<"RISCVISD::ROLW", SDT_RISCVIntBinOpW>;
def riscv_rorw : SDNode<"RISCVISD::RORW", SDT_RISCVIntBinOpW>;
-def riscv_grev : SDNode<"RISCVISD::GREV", SDTIntBinOp>;
-def riscv_grevw : SDNode<"RISCVISD::GREVW", SDT_RISCVIntBinOpW>;
-def riscv_gorc : SDNode<"RISCVISD::GORC", SDTIntBinOp>;
-def riscv_gorcw : SDNode<"RISCVISD::GORCW", SDT_RISCVIntBinOpW>;
-def riscv_shfl : SDNode<"RISCVISD::SHFL", SDTIntBinOp>;
-def riscv_shflw : SDNode<"RISCVISD::SHFLW", SDT_RISCVIntBinOpW>;
-def riscv_unshfl : SDNode<"RISCVISD::UNSHFL", SDTIntBinOp>;
-def riscv_unshflw: SDNode<"RISCVISD::UNSHFLW",SDT_RISCVIntBinOpW>;
+def riscv_brev8 : SDNode<"RISCVISD::BREV8", SDTIntUnaryOp>;
+def riscv_orc_b : SDNode<"RISCVISD::ORC_B", SDTIntUnaryOp>;
+def riscv_zip : SDNode<"RISCVISD::ZIP", SDTIntUnaryOp>;
+def riscv_unzip : SDNode<"RISCVISD::UNZIP", SDTIntUnaryOp>;
def riscv_bfp : SDNode<"RISCVISD::BFP", SDTIntBinOp>;
def riscv_bfpw : SDNode<"RISCVISD::BFPW", SDT_RISCVIntBinOpW>;
def riscv_bcompress : SDNode<"RISCVISD::BCOMPRESS", SDTIntBinOp>;
@@ -654,21 +650,17 @@ def : Pat<(and GPR:$r, BCLRIANDIMask:$i),
} // Predicates = [HasStdExtZbs]
let Predicates = [HasStdExtZbb] in {
-// We treat orc.b as a separate instruction, so match it directly. We also
-// lower the Zbb orc.b intrinsic to this.
-def : Pat<(riscv_gorc GPR:$rs1, 7), (ORC_B GPR:$rs1)>;
+def : Pat<(riscv_orc_b GPR:$rs1), (ORC_B GPR:$rs1)>;
} // Predicates = [HasStdExtZbb]
let Predicates = [HasStdExtZbkb] in {
-// We treat brev8 as a separate instruction, so match it directly. We also
-// use this for brev8 when lowering bitreverse with Zbkb.
-def : Pat<(riscv_grev GPR:$rs1, 7), (BREV8 GPR:$rs1)>;
+def : Pat<(riscv_brev8 GPR:$rs1), (BREV8 GPR:$rs1)>;
} // Predicates = [HasStdExtZbkb]
let Predicates = [HasStdExtZbkb, IsRV32] in {
// We treat zip and unzip as separate instructions, so match it directly.
-def : Pat<(i32 (riscv_shfl GPR:$rs1, 15)), (ZIP_RV32 GPR:$rs1)>;
-def : Pat<(i32 (riscv_unshfl GPR:$rs1, 15)), (UNZIP_RV32 GPR:$rs1)>;
+def : Pat<(i32 (riscv_zip GPR:$rs1)), (ZIP_RV32 GPR:$rs1)>;
+def : Pat<(i32 (riscv_unzip GPR:$rs1)), (UNZIP_RV32 GPR:$rs1)>;
} // Predicates = [HasStdExtZbkb, IsRV32]
let Predicates = [HasStdExtZbb] in {
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