[llvm] 1d8a7ad - [RISCV] Rename RISCVISD::SINT_TO_FP_VL/UINT_TO_FP_VL. NFC
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Wed Sep 21 15:36:22 PDT 2022
Author: Craig Topper
Date: 2022-09-21T15:33:04-07:00
New Revision: 1d8a7adca6afa479d2913189631d941e0b084825
URL: https://github.com/llvm/llvm-project/commit/1d8a7adca6afa479d2913189631d941e0b084825
DIFF: https://github.com/llvm/llvm-project/commit/1d8a7adca6afa479d2913189631d941e0b084825.diff
LOG: [RISCV] Rename RISCVISD::SINT_TO_FP_VL/UINT_TO_FP_VL. NFC
Name them after the instructions VFCVT_RTZ_X(U)_F_VL to make it
clear that the ISD nodes don't have the poison semantics of
ISD::SINT_TO_FP/UINT_TO_FP.
I play to reuse this node for a FP_TO_SINT_SAT/FP_TO_UINT_SAT
patch and need the instruction semantics.
Added:
Modified:
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
llvm/lib/Target/RISCV/RISCVISelLowering.h
llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 27c6aa15e3e7e..6cda6deadc421 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -1968,7 +1968,8 @@ lowerFTRUNC_FCEIL_FFLOOR_FROUND(SDValue Op, SelectionDAG &DAG,
break;
}
case ISD::FTRUNC:
- Truncated = DAG.getNode(RISCVISD::FP_TO_SINT_VL, DL, IntVT, Src, Mask, VL);
+ Truncated =
+ DAG.getNode(RISCVISD::VFCVT_RTZ_X_F_VL, DL, IntVT, Src, Mask, VL);
break;
}
@@ -3535,10 +3536,10 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
default:
llvm_unreachable("Impossible opcode");
case ISD::FP_TO_SINT:
- RVVOpc = RISCVISD::FP_TO_SINT_VL;
+ RVVOpc = RISCVISD::VFCVT_RTZ_X_F_VL;
break;
case ISD::FP_TO_UINT:
- RVVOpc = RISCVISD::FP_TO_UINT_VL;
+ RVVOpc = RISCVISD::VFCVT_RTZ_XU_F_VL;
break;
case ISD::SINT_TO_FP:
RVVOpc = RISCVISD::SINT_TO_FP_VL;
@@ -3868,9 +3869,9 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
case ISD::VP_FP_ROUND:
return lowerVectorFPExtendOrRoundLike(Op, DAG);
case ISD::VP_FP_TO_SINT:
- return lowerVPFPIntConvOp(Op, DAG, RISCVISD::FP_TO_SINT_VL);
+ return lowerVPFPIntConvOp(Op, DAG, RISCVISD::VFCVT_RTZ_X_F_VL);
case ISD::VP_FP_TO_UINT:
- return lowerVPFPIntConvOp(Op, DAG, RISCVISD::FP_TO_UINT_VL);
+ return lowerVPFPIntConvOp(Op, DAG, RISCVISD::VFCVT_RTZ_XU_F_VL);
case ISD::VP_SINT_TO_FP:
return lowerVPFPIntConvOp(Op, DAG, RISCVISD::SINT_TO_FP_VL);
case ISD::VP_UINT_TO_FP:
@@ -6576,11 +6577,6 @@ SDValue RISCVTargetLowering::lowerVPFPIntConvOp(SDValue Op, SelectionDAG &DAG,
Mask = convertToScalableVector(MaskVT, Mask, DAG, Subtarget);
}
- unsigned RISCVISDExtOpc = (RISCVISDOpc == RISCVISD::SINT_TO_FP_VL ||
- RISCVISDOpc == RISCVISD::FP_TO_SINT_VL)
- ? RISCVISD::VSEXT_VL
- : RISCVISD::VZEXT_VL;
-
unsigned DstEltSize = DstVT.getScalarSizeInBits();
unsigned SrcEltSize = SrcVT.getScalarSizeInBits();
@@ -6589,6 +6585,10 @@ SDValue RISCVTargetLowering::lowerVPFPIntConvOp(SDValue Op, SelectionDAG &DAG,
if (SrcVT.isInteger()) {
assert(DstVT.isFloatingPoint() && "Wrong input/output vector types");
+ unsigned RISCVISDExtOpc = RISCVISDOpc == RISCVISD::SINT_TO_FP_VL
+ ? RISCVISD::VSEXT_VL
+ : RISCVISD::VZEXT_VL;
+
// Do we need to do any pre-widening before converting?
if (SrcEltSize == 1) {
MVT IntVT = DstVT.changeVectorElementTypeToInteger();
@@ -12289,8 +12289,8 @@ const char *RISCVTargetLowering::getTargetNodeName(unsigned Opcode) const {
NODE_NAME_CASE(FMAXNUM_VL)
NODE_NAME_CASE(MULHS_VL)
NODE_NAME_CASE(MULHU_VL)
- NODE_NAME_CASE(FP_TO_SINT_VL)
- NODE_NAME_CASE(FP_TO_UINT_VL)
+ NODE_NAME_CASE(VFCVT_RTZ_X_F_VL)
+ NODE_NAME_CASE(VFCVT_RTZ_XU_F_VL)
NODE_NAME_CASE(VFCVT_X_F_VL)
NODE_NAME_CASE(SINT_TO_FP_VL)
NODE_NAME_CASE(UINT_TO_FP_VL)
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.h b/llvm/lib/Target/RISCV/RISCVISelLowering.h
index 42e053d1b9ef9..d019fa3230e5f 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.h
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.h
@@ -244,9 +244,9 @@ enum NodeType : unsigned {
FABS_VL,
FSQRT_VL,
FCOPYSIGN_VL, // Has a merge operand
- FP_TO_SINT_VL,
- FP_TO_UINT_VL,
- VFCVT_X_F_VL,
+ VFCVT_RTZ_X_F_VL,
+ VFCVT_RTZ_XU_F_VL,
+ VFCVT_X_F_VL, // Has a rounding mode operand.
SINT_TO_FP_VL,
UINT_TO_FP_VL,
FP_ROUND_VL,
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
index 3a72c96ae8af8..2c4e228264428 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
@@ -141,8 +141,8 @@ def SDT_RISCVI2FPOp_VL : SDTypeProfile<1, 3, [
SDTCVecEltisVT<2, i1>, SDTCisSameNumEltsAs<1, 2>, SDTCisVT<3, XLenVT>
]>;
-def riscv_fp_to_sint_vl : SDNode<"RISCVISD::FP_TO_SINT_VL", SDT_RISCVFP2IOp_VL>;
-def riscv_fp_to_uint_vl : SDNode<"RISCVISD::FP_TO_UINT_VL", SDT_RISCVFP2IOp_VL>;
+def riscv_vfcvt_rtz_x_f_vl : SDNode<"RISCVISD::VFCVT_RTZ_X_F_VL", SDT_RISCVFP2IOp_VL>;
+def riscv_vfcvt_rtz_xu_f_vl : SDNode<"RISCVISD::VFCVT_RTZ_XU_F_VL", SDT_RISCVFP2IOp_VL>;
def riscv_sint_to_fp_vl : SDNode<"RISCVISD::SINT_TO_FP_VL", SDT_RISCVI2FPOp_VL>;
def riscv_uint_to_fp_vl : SDNode<"RISCVISD::UINT_TO_FP_VL", SDT_RISCVI2FPOp_VL>;
@@ -1523,14 +1523,14 @@ foreach fvti = AllFloatVectors in {
// 14.17. Vector Single-Width Floating-Point/Integer Type-Convert Instructions
defm : VPatConvertFP2I_RM_VL_V<riscv_vfcvt_x_f_vl, "PseudoVFCVT_RM_X_F_V">;
- defm : VPatConvertFP2IVL_V<riscv_fp_to_sint_vl, "PseudoVFCVT_RTZ_X_F_V">;
- defm : VPatConvertFP2IVL_V<riscv_fp_to_uint_vl, "PseudoVFCVT_RTZ_XU_F_V">;
+ defm : VPatConvertFP2IVL_V<riscv_vfcvt_rtz_x_f_vl, "PseudoVFCVT_RTZ_X_F_V">;
+ defm : VPatConvertFP2IVL_V<riscv_vfcvt_rtz_xu_f_vl, "PseudoVFCVT_RTZ_XU_F_V">;
defm : VPatConvertI2FPVL_V<riscv_sint_to_fp_vl, "PseudoVFCVT_F_X_V">;
defm : VPatConvertI2FPVL_V<riscv_uint_to_fp_vl, "PseudoVFCVT_F_XU_V">;
// 14.18. Widening Floating-Point/Integer Type-Convert Instructions
- defm : VPatWConvertFP2IVL_V<riscv_fp_to_sint_vl, "PseudoVFWCVT_RTZ_X_F_V">;
- defm : VPatWConvertFP2IVL_V<riscv_fp_to_uint_vl, "PseudoVFWCVT_RTZ_XU_F_V">;
+ defm : VPatWConvertFP2IVL_V<riscv_vfcvt_rtz_x_f_vl, "PseudoVFWCVT_RTZ_X_F_V">;
+ defm : VPatWConvertFP2IVL_V<riscv_vfcvt_rtz_xu_f_vl, "PseudoVFWCVT_RTZ_XU_F_V">;
defm : VPatWConvertI2FPVL_V<riscv_sint_to_fp_vl, "PseudoVFWCVT_F_X_V">;
defm : VPatWConvertI2FPVL_V<riscv_uint_to_fp_vl, "PseudoVFWCVT_F_XU_V">;
foreach fvtiToFWti = AllWidenableFloatVectors in {
@@ -1545,8 +1545,8 @@ foreach fvti = AllFloatVectors in {
}
// 14.19 Narrowing Floating-Point/Integer Type-Convert Instructions
- defm : VPatNConvertFP2IVL_V<riscv_fp_to_sint_vl, "PseudoVFNCVT_RTZ_X_F_W">;
- defm : VPatNConvertFP2IVL_V<riscv_fp_to_uint_vl, "PseudoVFNCVT_RTZ_XU_F_W">;
+ defm : VPatNConvertFP2IVL_V<riscv_vfcvt_rtz_x_f_vl, "PseudoVFNCVT_RTZ_X_F_W">;
+ defm : VPatNConvertFP2IVL_V<riscv_vfcvt_rtz_xu_f_vl, "PseudoVFNCVT_RTZ_XU_F_W">;
defm : VPatNConvertI2FPVL_V<riscv_sint_to_fp_vl, "PseudoVFNCVT_F_X_W">;
defm : VPatNConvertI2FPVL_V<riscv_uint_to_fp_vl, "PseudoVFNCVT_F_XU_W">;
foreach fvtiToFWti = AllWidenableFloatVectors in {
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