[llvm] 1f4d3c6 - [NFC][AMDGPU] Add new v_bfi Codegen test.

[Thomas Symalla via llvm-commits]

Author: Thomas Symalla
Date: 2022-09-21T19:02:11+02:00
New Revision: 1f4d3c681c9552f9b0327a9c6d9db6c2153fc459

URL: https://github.com/llvm/llvm-project/commit/1f4d3c681c9552f9b0327a9c6d9db6c2153fc459
DIFF: https://github.com/llvm/llvm-project/commit/1f4d3c681c9552f9b0327a9c6d9db6c2153fc459.diff

LOG: [NFC][AMDGPU] Add new v_bfi Codegen test.

Pre-commit a test for an upcoming change.

Added: 
    

Modified: 
    llvm/test/CodeGen/AMDGPU/bfi_int.ll

Removed: 
    


################################################################################
diff  --git a/llvm/test/CodeGen/AMDGPU/bfi_int.ll b/llvm/test/CodeGen/AMDGPU/bfi_int.ll
index 6c0a183289e1f..c61c53e1823b0 100644
--- a/llvm/test/CodeGen/AMDGPU/bfi_int.ll
+++ b/llvm/test/CodeGen/AMDGPU/bfi_int.ll
@@ -1907,3 +1907,61 @@ entry:
   store i64 %scalar.use, i64 addrspace(1)* undef
   ret void
 }
+
+define i32 @v_bfi_seq_i32(i32 %x, i32 %y, i32 %z) {
+; GFX7-LABEL: v_bfi_seq_i32:
+; GFX7:       ; %bb.0:
+; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX7-NEXT:    s_mov_b32 s4, 0xffc00
+; GFX7-NEXT:    v_bfi_b32 v0, s4, v0, v1
+; GFX7-NEXT:    v_xor_b32_e32 v1, v1, v2
+; GFX7-NEXT:    v_and_b32_e32 v1, 0x3ff00000, v1
+; GFX7-NEXT:    v_xor_b32_e32 v0, v1, v0
+; GFX7-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX8-LABEL: v_bfi_seq_i32:
+; GFX8:       ; %bb.0:
+; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT:    s_mov_b32 s4, 0xffc00
+; GFX8-NEXT:    v_bfi_b32 v0, s4, v0, v1
+; GFX8-NEXT:    v_xor_b32_e32 v1, v1, v2
+; GFX8-NEXT:    v_and_b32_e32 v1, 0x3ff00000, v1
+; GFX8-NEXT:    v_xor_b32_e32 v0, v1, v0
+; GFX8-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: v_bfi_seq_i32:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX10-NEXT:    v_xor_b32_e32 v2, v1, v2
+; GFX10-NEXT:    v_bfi_b32 v0, 0xffc00, v0, v1
+; GFX10-NEXT:    v_and_b32_e32 v1, 0x3ff00000, v2
+; GFX10-NEXT:    v_xor_b32_e32 v0, v1, v0
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX8-GISEL-LABEL: v_bfi_seq_i32:
+; GFX8-GISEL:       ; %bb.0:
+; GFX8-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-GISEL-NEXT:    v_and_b32_e32 v0, 0xffc00, v0
+; GFX8-GISEL-NEXT:    v_and_b32_e32 v1, 0xfff003ff, v1
+; GFX8-GISEL-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX8-GISEL-NEXT:    v_mov_b32_e32 v1, 0x3ff00000
+; GFX8-GISEL-NEXT:    v_bfi_b32 v0, v1, v2, v0
+; GFX8-GISEL-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX10-GISEL-LABEL: v_bfi_seq_i32:
+; GFX10-GISEL:       ; %bb.0:
+; GFX10-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-GISEL-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX10-GISEL-NEXT:    v_and_b32_e32 v1, 0xfff003ff, v1
+; GFX10-GISEL-NEXT:    v_and_or_b32 v0, 0xffc00, v0, v1
+; GFX10-GISEL-NEXT:    v_bfi_b32 v0, 0x3ff00000, v2, v0
+; GFX10-GISEL-NEXT:    s_setpc_b64 s[30:31]
+  %1 = and i32 %x, 1047552
+  %2 = and i32 %y, -1047553
+  %3 = or i32 %1, %2
+  %4 = xor i32 %3, %z
+  %5 = and i32 %4, 1072693248
+  %6 = xor i32 %5, %3
+  ret i32 %6
+}