[PATCH] D134366: MachineVerifier: Verify REG_SEQUENCE

[Matt Arsenault via Phabricator via llvm-commits]

arsenm created this revision.
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Somehow there was no verification of this, other than an ad-hoc
assertion in TwoAddressInstructions.


https://reviews.llvm.org/D134366

Files:
  llvm/lib/CodeGen/MachineOperand.cpp
  llvm/lib/CodeGen/MachineVerifier.cpp
  llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
  llvm/test/CodeGen/AMDGPU/load-store-opt-scc.mir
  llvm/test/CodeGen/MIR/AMDGPU/load-store-opt-dlc.mir
  llvm/test/CodeGen/MIR/X86/subregister-index-operands.mir
  llvm/test/MachineVerifier/verify-reg-sequence.mir

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