[llvm] ddd27a3 - [AArch64] add tests for fadd -> fma combines; NFC

[Sanjay Patel via llvm-commits]

Author: Sanjay Patel
Date: 2022-09-21T09:00:11-04:00
New Revision: ddd27a3d39344ce1f13316227eb176c7672a583c

URL: https://github.com/llvm/llvm-project/commit/ddd27a3d39344ce1f13316227eb176c7672a583c
DIFF: https://github.com/llvm/llvm-project/commit/ddd27a3d39344ce1f13316227eb176c7672a583c.diff

LOG: [AArch64] add tests for fadd -> fma combines; NFC

The transform to create a final fma was added with:
D132837 / c98a46fee6f4043276eac

These tests are intended to show the minimal fast-math-flags
necessary to enable the fold: currently only the final fadd
needs to have "reassoc".

Added: 
    

Modified: 
    llvm/test/CodeGen/AArch64/fadd-combines.ll

Removed: 
    


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diff  --git a/llvm/test/CodeGen/AArch64/fadd-combines.ll b/llvm/test/CodeGen/AArch64/fadd-combines.ll
index 8807df1fa64c..44dc680324df 100644
--- a/llvm/test/CodeGen/AArch64/fadd-combines.ll
+++ b/llvm/test/CodeGen/AArch64/fadd-combines.ll
@@ -315,5 +315,37 @@ define float @fadd_fma_fmul_extra_use_3(float %a, float %b, float %c, float %d,
   ret float %a2
 }
 
+define float @fmac_sequence_innermost_fmul(float %a, float %b, float %c, float %d, float %e, float %f, float %g) {
+; CHECK-LABEL: fmac_sequence_innermost_fmul:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    fmadd s0, s0, s1, s6
+; CHECK-NEXT:    fmadd s0, s2, s3, s0
+; CHECK-NEXT:    fmadd s0, s4, s5, s0
+; CHECK-NEXT:    ret
+  %t0 = fmul float %a, %b
+  %t1 = fmul contract float %c, %d
+  %t2 = fadd contract float %t0, %t1
+  %t3 = fmul contract float %e, %f
+  %t4 = fadd contract float %t2, %t3
+  %t5 = fadd contract reassoc float %t4, %g
+  ret float %t5
+}
+
+define float @fmac_sequence_innermost_fmul_intrinsics(float %a, float %b, float %c, float %d, float %e, float %f, float %g) {
+; CHECK-LABEL: fmac_sequence_innermost_fmul_intrinsics:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    fmadd s0, s0, s1, s6
+; CHECK-NEXT:    fmadd s0, s2, s3, s0
+; CHECK-NEXT:    fmadd s0, s4, s5, s0
+; CHECK-NEXT:    ret
+  %t0 = fmul float %a, %b
+  %t1 = call float @llvm.fma.f32(float %c, float %d, float %t0)
+  %t2 = call float @llvm.fma.f32(float %e, float %f, float %t1)
+  %t5 = fadd contract reassoc float %t2, %g
+  ret float %t5
+}
+
+declare float @llvm.fma.f32(float, float, float)
+
 declare void @use(double)